ram: Ack stores early

Stores only need a single cycle, so we can ack them early if there
isn't an older ack already in the pipeline

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

wishbone_bram_wrapper.vhdl

@@ -66,11 +66,19 @@ begin
 	    if rst = '1' or wishbone_in.cyc = '0' then
 		ack_buf <= '0';
 		ack <= '0';
+	    else
+		-- On loads, we have a delay cycle due to BRAM bufferring
+		-- but not on stores. So try to send an early ack on a
+		-- store if we aren't behind an existing load ack.
+		--
+		if ram_we = '1' and ack = '0' then
+		    ack_buf <= '1';
 		else
 		    ack <= wishbone_in.stb;
 		    ack_buf <= ack;
 		end if;
 	    end if;
+	end if;
     end process;
 
 end architecture behaviour;