simple_ram: Turn on pipelining

With a 1 cycle delay

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
jtag-port
Benjamin Herrenschmidt 5 years ago
parent c22734d0d9
commit 365f60b693

@ -11,7 +11,7 @@ entity mw_soc_memory is
generic ( generic (
RAM_INIT_FILE : string; RAM_INIT_FILE : string;
MEMORY_SIZE : integer; MEMORY_SIZE : integer;
PIPELINE_DEPTH : integer := 0 PIPELINE_DEPTH : integer := 1
); );


port ( port (

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