forked from cores/microwatt
Anton Blanchard
5 years ago
committed by
GitHub
commit
4160f2138d
Binary file not shown.
@ -0,0 +1,3 @@
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Test 0:PASS
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Test 1:PASS
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Test 2:PASS
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@ -0,0 +1,5 @@
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TEST=xics
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include ../Makefile.test
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xics.o : xics.h
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@ -0,0 +1,186 @@
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/* Copyright 2013-2014 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define STACK_TOP 0x4000
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/* Load an immediate 64-bit value into a register */
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#define LOAD_IMM64(r, e) \
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lis r,(e)@highest; \
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ori r,r,(e)@higher; \
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rldicr r,r, 32, 31; \
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oris r,r, (e)@h; \
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ori r,r, (e)@l;
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.section ".head","ax"
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/* Microwatt currently enters in LE mode at 0x0 */
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. = 0
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.global _start
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_start:
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LOAD_IMM64(%r12, 0x000000000ffffff)
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mtdec %r12
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LOAD_IMM64(%r12, 0x9000000000008003)
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mtmsrd %r12 // EE on
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/* setup stack */
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LOAD_IMM64(%r1, STACK_TOP - 0x100)
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LOAD_IMM64(%r12, main)
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mtctr %r12
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bctrl
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attn // terminate on exit
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b .
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#define EXCEPTION(nr) \
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.= nr ;\
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b .
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/* More exception stubs */
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EXCEPTION(0x300)
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EXCEPTION(0x380)
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EXCEPTION(0x400)
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EXCEPTION(0x480)
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. = 0x500
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b __isr
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EXCEPTION(0x600)
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EXCEPTION(0x700)
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EXCEPTION(0x800)
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EXCEPTION(0x900)
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EXCEPTION(0x980)
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EXCEPTION(0xa00)
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EXCEPTION(0xb00)
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EXCEPTION(0xc00)
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EXCEPTION(0xd00)
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// ISR data
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#define REDZONE_SIZE (512)
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#define REG_SAVE_SIZE ((32 + 5)*8)
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#define STACK_FRAME_C_MINIMAL 64
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#define SAVE_NIA (32*8)
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#define SAVE_LR (33*8)
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#define SAVE_CTR (34*8)
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#define SAVE_CR (35*8)
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#define SAVE_SRR1 (36*8)
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__isr:
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/*
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* Assume where we are coming from has a stack and can save there.
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* We save the full register set. Since we are calling out to C, we
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* could just save the ABI volatile registers
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*/
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stdu %r1,-(REG_SAVE_SIZE+REDZONE_SIZE)(%r1)
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std %r0, 1*8(%r1)
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// std %r1, 1*8(%r1)
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std %r2, 2*8(%r1)
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std %r3, 3*8(%r1)
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std %r4, 4*8(%r1)
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std %r5, 5*8(%r1)
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std %r6, 6*8(%r1)
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std %r7, 7*8(%r1)
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std %r8, 8*8(%r1)
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std %r9, 9*8(%r1)
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std %r10, 10*8(%r1)
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std %r11, 11*8(%r1)
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std %r12, 12*8(%r1)
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std %r13, 13*8(%r1)
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std %r14, 14*8(%r1)
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std %r15, 15*8(%r1)
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std %r16, 16*8(%r1)
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std %r17, 17*8(%r1)
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std %r18, 18*8(%r1)
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std %r19, 19*8(%r1)
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std %r20, 20*8(%r1)
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std %r21, 21*8(%r1)
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std %r22, 22*8(%r1)
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std %r23, 23*8(%r1)
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std %r24, 24*8(%r1)
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std %r25, 25*8(%r1)
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std %r26, 26*8(%r1)
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std %r27, 27*8(%r1)
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std %r28, 28*8(%r1)
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std %r29, 29*8(%r1)
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std %r30, 30*8(%r1)
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std %r31, 31*8(%r1)
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mfsrr0 %r0
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std %r0, SAVE_NIA*8(%r1)
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mflr %r0
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std %r0, SAVE_LR*8(%r1)
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mfctr %r0
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std %r0, SAVE_CTR*8(%r1)
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mfcr %r0
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std %r0, SAVE_CR*8(%r1)
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mfsrr1 %r0
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std %r0, SAVE_SRR1*8(%r1)
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stdu %r1,-STACK_FRAME_C_MINIMAL(%r1)
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LOAD_IMM64(%r3, isr)
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mtctr %r3,
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bctrl
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nop
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ld %r1, 0(%r1)
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ld %r0, 1*8(%r1)
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// ld %r1, 1*8(%r1) // do this at rfid
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ld %r2, 2*8(%r1)
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// ld %r3, 3*8(%r1) // do this at rfid
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ld %r4, 4*8(%r1)
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ld %r5, 5*8(%r1)
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ld %r6, 6*8(%r1)
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ld %r7, 7*8(%r1)
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ld %r8, 8*8(%r1)
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ld %r9, 9*8(%r1)
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ld %r10, 10*8(%r1)
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ld %r11, 11*8(%r1)
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ld %r12, 12*8(%r1)
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ld %r13, 13*8(%r1)
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ld %r14, 14*8(%r1)
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ld %r15, 15*8(%r1)
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ld %r16, 16*8(%r1)
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ld %r17, 17*8(%r1)
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ld %r18, 18*8(%r1)
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ld %r19, 19*8(%r1)
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ld %r20, 20*8(%r1)
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ld %r21, 21*8(%r1)
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ld %r22, 22*8(%r1)
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ld %r23, 23*8(%r1)
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ld %r24, 24*8(%r1)
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ld %r25, 25*8(%r1)
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ld %r26, 26*8(%r1)
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ld %r27, 27*8(%r1)
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ld %r28, 28*8(%r1)
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ld %r29, 29*8(%r1)
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ld %r30, 30*8(%r1)
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ld %r31, 31*8(%r1)
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ld %r3, SAVE_LR*8(%r1)
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mtlr %r3
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ld %r3, SAVE_CTR*8(%r1)
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mtctr %r3
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ld %r3, SAVE_CR*8(%r1)
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mtcr %r3
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ld %r3, SAVE_SRR1*8(%r1)
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mtsrr1 %r3
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ld %r3, SAVE_NIA*8(%r1)
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mtsrr0 %r3
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/* restore %r3 */
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ld %r3, 3*8(%r1)
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/* do final fixup r1 */
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ld %r1, 0*8(%r1)
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rfid
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@ -0,0 +1,13 @@
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SECTIONS
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{
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_start = .;
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. = 0;
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.head : {
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KEEP(*(.head))
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}
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. = 0x1000;
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.text : { *(.text) }
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. = 0x3000;
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.data : { *(.data) }
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.bss : { *(.bss) }
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}
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@ -0,0 +1,262 @@
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <limits.h>
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#include "console.h"
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#include "xics.h"
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#undef DEBUG
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//#define DEBUG 1
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void print_number(unsigned int i) // only for i = 0-999
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{
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unsigned int j, k, m;
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bool zeros = false;
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k = 1000000000;
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for (m = 0; m < 10 ; m++) {
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j = i/k;
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if (m == 9) zeros = true;
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if (zeros || (j != 0)) {
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putchar(48 + j);
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zeros = true;
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}
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i = i % k;
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k = k / 10;
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}
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}
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#ifdef DEBUG
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#define DEBUG_STR "\r\nDEBUG: "
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void debug_print(int i)
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{
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putstr(DEBUG_STR, strlen(DEBUG_STR));
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print_number(i);
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putstr("\r\n", 2);
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}
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#define debug_putstr(a, b) putstr(a,b)
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#else
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#define debug_putstr(a, b)
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#define debug_print(i)
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#endif
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#define ASSERT_FAIL "() ASSERT_FAILURE!\r\n "
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#define assert(cond) \
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if (!(cond)) { \
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putstr(__FILE__, strlen(__FILE__)); \
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putstr(":", 1); \
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print_number(__LINE__); \
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putstr(":", 1); \
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putstr(__FUNCTION__, strlen(__FUNCTION__));\
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putstr(ASSERT_FAIL, strlen(ASSERT_FAIL)); \
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__asm__ ("attn"); \
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}
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volatile uint64_t isrs_run;
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#define ISR_IPI 0x0000000000000001
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#define ISR_UART 0x0000000000000002
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#define ISR_SPURIOUS 0x0000000000000004
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#define IPI "IPI\r\n"
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void ipi_isr(void) {
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debug_putstr(IPI, strlen(IPI));
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isrs_run |= ISR_IPI;
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}
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#define UART "UART\r\n"
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void uart_isr(void) {
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debug_putstr(UART, strlen(UART));
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potato_uart_irq_dis(); // disable interrupt to ack it
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isrs_run |= ISR_UART;
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}
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// The hardware doesn't support this but it's part of XICS so add it.
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#define SPURIOUS "SPURIOUS\r\n"
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void spurious_isr(void) {
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debug_putstr(SPURIOUS, strlen(SPURIOUS));
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isrs_run |= ISR_SPURIOUS;
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}
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struct isr_op {
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void (*func)(void);
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int source_id;
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};
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struct isr_op isr_table[] = {
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{ .func = ipi_isr, .source_id = 2 },
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{ .func = uart_isr, .source_id = 16 },
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{ .func = spurious_isr, .source_id = 0 },
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{ .func = NULL, .source_id = 0 }
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};
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bool ipi_running;
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#define ISR "ISR XISR="
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void isr(void)
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{
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struct isr_op *op;
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uint32_t xirr;
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assert(!ipi_running); // check we aren't reentrant
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ipi_running = true;
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xirr = xics_read32(XICS_XIRR); // read hardware irq source
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#ifdef DEBUG
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putstr(ISR, strlen(ISR));
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print_number(xirr & 0xff);
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putstr("\r\n", 2);
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#endif
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op = isr_table;
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while (1) {
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assert(op->func); // didn't find isr
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if (op->source_id == (xirr & 0x00ffffff)) {
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op->func();
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break;
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}
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op++;
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}
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xics_write32(XICS_XIRR, xirr); // EOI
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ipi_running = false;
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}
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/*****************************************/
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int xics_test_0(void)
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{
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// setup
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xics_write8(XICS_XIRR, 0x00); // mask all interrupts
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isrs_run = 0;
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xics_write8(XICS_XIRR, 0x00); // mask all interrupts
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// trigger two interrupts
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potato_uart_irq_en(); // cause 0x500 interrupt
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xics_write8(XICS_MFRR, 0x05); // cause 0x500 interrupt
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// still masked, so shouldn't happen yet
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assert(isrs_run == 0);
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// unmask IPI only
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xics_write8(XICS_XIRR, 0x40);
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assert(isrs_run == ISR_IPI);
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// unmask UART
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xics_write8(XICS_XIRR, 0xc0);
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assert(isrs_run == (ISR_IPI | ISR_UART));
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// cleanup
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xics_write8(XICS_XIRR, 0x00); // mask all interrupts
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isrs_run = 0;
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return 0;
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}
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int xics_test_1(void)
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{
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// setup
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xics_write8(XICS_XIRR, 0x00); // mask all interrupts
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isrs_run = 0;
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xics_write8(XICS_XIRR, 0xff); // allow all interrupts
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// should be none pending
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assert(isrs_run == 0);
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// trigger both
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potato_uart_irq_en(); // cause 0x500 interrupt
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xics_write8(XICS_MFRR, 0x05); // cause 0x500 interrupt
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assert(isrs_run == (ISR_IPI | ISR_UART));
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// cleanup
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xics_write8(XICS_XIRR, 0x00); // mask all interrupts
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isrs_run = 0;
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return 0;
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}
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void mtmsrd(uint64_t val)
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{
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__asm__ volatile("mtmsrd %0" : : "r" (val));
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}
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int xics_test_2(void)
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{
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// setup
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xics_write8(XICS_XIRR, 0x00); // mask all interrupts
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isrs_run = 0;
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// trigger interrupts with MSR[EE]=0 and show they are not run
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mtmsrd(0x9000000000000003); // EE off
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xics_write8(XICS_XIRR, 0xff); // allow all interrupts
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// trigger an IPI
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xics_write8(XICS_MFRR, 0x05); // cause 0x500 interrupt
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assert(isrs_run == 0);
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mtmsrd(0x9000000000008003); // EE on
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assert(isrs_run == ISR_IPI);
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// cleanup
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xics_write8(XICS_XIRR, 0x00); // mask all interrupts
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isrs_run = 0;
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return 0;
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}
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#define TEST "Test "
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#define PASS "PASS\r\n"
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#define FAIL "FAIL\r\n"
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int (*tests[])(void) = {
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xics_test_0,
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xics_test_1,
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xics_test_2,
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NULL
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};
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int main(void)
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{
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int fail = 0;
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int i = 0;
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int (*t)(void);
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potato_uart_init();
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ipi_running = false;
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/* run the tests */
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while (1) {
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t = tests[i];
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if (!t)
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break;
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putstr(TEST, strlen(TEST));
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print_number(i);
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putstr(": ", 1);
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if (t() != 0) {
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fail = 1;
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putstr(FAIL, strlen(FAIL));
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} else
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putstr(PASS, strlen(PASS));
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i++;
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}
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return fail;
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}
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@ -0,0 +1,36 @@
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#include <stdint.h>
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#define XICS_BASE 0xc0004000
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static uint64_t xics_base = XICS_BASE;
|
||||
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||||
#define XICS_XIRR_POLL 0x0
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#define XICS_XIRR 0x4
|
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#define XICS_RESV 0x8
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#define XICS_MFRR 0xC
|
||||
|
||||
uint8_t xics_read8(int offset)
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{
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||||
uint32_t val;
|
||||
|
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__asm__ volatile("lbzcix %0,%1,%2" : "=r" (val) : "b" (xics_base), "r" (offset));
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return val;
|
||||
}
|
||||
|
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void xics_write8(int offset, uint8_t val)
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{
|
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__asm__ volatile("stbcix %0,%1,%2" : : "r" (val), "b" (xics_base), "r" (offset));
|
||||
}
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||||
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uint32_t xics_read32(int offset)
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{
|
||||
uint32_t val;
|
||||
|
||||
__asm__ volatile("lwzcix %0,%1,%2" : "=r" (val) : "b" (xics_base), "r" (offset));
|
||||
return val;
|
||||
}
|
||||
|
||||
void xics_write32(int offset, uint32_t val)
|
||||
{
|
||||
__asm__ volatile("stwcix %0,%1,%2" : : "r" (val), "b" (xics_base), "r" (offset));
|
||||
}
|
||||
@ -0,0 +1,207 @@
|
||||
--
|
||||
-- This is a simple XICS compliant interrupt controller. This is a
|
||||
-- Presenter (ICP) and Source (ICS) in a single unit with no routing
|
||||
-- layer.
|
||||
--
|
||||
-- The sources have a fixed IRQ priority set by HW_PRIORITY. The
|
||||
-- source id starts at 16 for int_level_in(0) and go up from
|
||||
-- there (ie int_level_in(1) is source id 17).
|
||||
--
|
||||
-- The presentation layer will pick an interupt that is more
|
||||
-- favourable than the current CPPR and present it via the XISR and
|
||||
-- send an interrpt to the processor (via e_out). This may not be the
|
||||
-- highest priority interrupt currently presented (which is allowed
|
||||
-- via XICS)
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.common.all;
|
||||
use work.wishbone_types.all;
|
||||
|
||||
entity xics is
|
||||
generic (
|
||||
LEVEL_NUM : positive := 16
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
||||
wb_in : in wishbone_master_out;
|
||||
wb_out : out wishbone_slave_out;
|
||||
|
||||
int_level_in : in std_ulogic_vector(LEVEL_NUM - 1 downto 0);
|
||||
|
||||
e_out : out XicsToExecute1Type
|
||||
);
|
||||
end xics;
|
||||
|
||||
architecture behaviour of xics is
|
||||
type reg_internal_t is record
|
||||
xisr : std_ulogic_vector(23 downto 0);
|
||||
cppr : std_ulogic_vector(7 downto 0);
|
||||
pending_priority : std_ulogic_vector(7 downto 0);
|
||||
mfrr : std_ulogic_vector(7 downto 0);
|
||||
mfrr_pending : std_ulogic;
|
||||
irq : std_ulogic;
|
||||
wb_rd_data : wishbone_data_type;
|
||||
wb_ack : std_ulogic;
|
||||
end record;
|
||||
constant reg_internal_init : reg_internal_t :=
|
||||
(wb_ack => '0',
|
||||
mfrr_pending => '0',
|
||||
mfrr => x"00", -- mask everything on reset
|
||||
irq => '0',
|
||||
others => (others => '0'));
|
||||
|
||||
signal r, r_next : reg_internal_t;
|
||||
|
||||
-- hardwire the hardware IRQ priority
|
||||
constant HW_PRIORITY : std_ulogic_vector(7 downto 0) := x"80";
|
||||
|
||||
-- 32 bit offsets for each presentation
|
||||
constant XIRR_POLL : std_ulogic_vector(31 downto 0) := x"00000000";
|
||||
constant XIRR : std_ulogic_vector(31 downto 0) := x"00000004";
|
||||
constant RESV0 : std_ulogic_vector(31 downto 0) := x"00000008";
|
||||
constant MFRR : std_ulogic_vector(31 downto 0) := x"0000000c";
|
||||
|
||||
begin
|
||||
|
||||
regs : process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
r <= r_next;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
wb_out.dat <= r.wb_rd_data;
|
||||
wb_out.ack <= r.wb_ack;
|
||||
wb_out.stall <= '0'; -- never stall wishbone
|
||||
e_out.irq <= r.irq;
|
||||
|
||||
comb : process(all)
|
||||
variable v : reg_internal_t;
|
||||
variable xirr_accept_rd : std_ulogic;
|
||||
variable irq_eoi : std_ulogic;
|
||||
begin
|
||||
v := r;
|
||||
|
||||
v.wb_ack := '0';
|
||||
|
||||
xirr_accept_rd := '0';
|
||||
irq_eoi := '0';
|
||||
|
||||
if wb_in.cyc = '1' and wb_in.stb = '1' then
|
||||
-- wishbone addresses we get are 64 bit alligned, so we
|
||||
-- need to use the sel bits to get 32 bit chunks.
|
||||
v.wb_ack := '1'; -- always ack
|
||||
if wb_in.we = '1' then -- write
|
||||
-- writes to both XIRR are the same
|
||||
if wb_in.adr = XIRR_POLL then
|
||||
report "XICS XIRR_POLL/XIRR write";
|
||||
if wb_in.sel = x"0f" then -- 4 bytes
|
||||
v.cppr := wb_in.dat(31 downto 24);
|
||||
elsif wb_in.sel = x"f0" then -- 4 byte
|
||||
v.cppr := wb_in.dat(63 downto 56);
|
||||
irq_eoi := '1';
|
||||
elsif wb_in.sel = x"01" then -- 1 byte
|
||||
v.cppr := wb_in.dat(7 downto 0);
|
||||
elsif wb_in.sel = x"10" then -- 1 byte
|
||||
v.cppr := wb_in.dat(39 downto 32);
|
||||
end if;
|
||||
|
||||
elsif wb_in.adr = RESV0 then
|
||||
report "XICS MFRR write";
|
||||
if wb_in.sel = x"f0" then -- 4 bytes
|
||||
v.mfrr_pending := '1';
|
||||
v.mfrr := wb_in.dat(63 downto 56);
|
||||
elsif wb_in.sel = x"10" then -- 1 byte
|
||||
v.mfrr_pending := '1';
|
||||
v.mfrr := wb_in.dat(39 downto 32);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
else -- read
|
||||
v.wb_rd_data := (others => '0');
|
||||
|
||||
if wb_in.adr = XIRR_POLL then
|
||||
report "XICS XIRR_POLL/XIRR read";
|
||||
if wb_in.sel = x"0f" then
|
||||
v.wb_rd_data(23 downto 0) := r.xisr;
|
||||
v.wb_rd_data(31 downto 24) := r.cppr;
|
||||
elsif wb_in.sel = x"f0" then
|
||||
v.wb_rd_data(55 downto 32) := r.xisr;
|
||||
v.wb_rd_data(63 downto 56) := r.cppr;
|
||||
xirr_accept_rd := '1';
|
||||
elsif wb_in.sel = x"01" then
|
||||
v.wb_rd_data(7 downto 0) := r.cppr;
|
||||
elsif wb_in.sel = x"10" then
|
||||
v.wb_rd_data(39 downto 32) := r.cppr;
|
||||
end if;
|
||||
|
||||
elsif wb_in.adr = RESV0 then
|
||||
report "XICS MFRR read";
|
||||
if wb_in.sel = x"f0" then -- 4 bytes
|
||||
v.wb_rd_data(63 downto 56) := r.mfrr;
|
||||
elsif wb_in.sel = x"10" then -- 1 byte
|
||||
v.wb_rd_data( 7 downto 0) := r.mfrr;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- generate interrupt
|
||||
if r.irq = '0' then
|
||||
-- Here we just present any interrupt that's valid and
|
||||
-- below cppr. For ordering, we ignore hardware
|
||||
-- priorities.
|
||||
if unsigned(HW_PRIORITY) < unsigned(r.cppr) then --
|
||||
-- lower HW sources are higher priority
|
||||
for i in LEVEL_NUM - 1 downto 0 loop
|
||||
if int_level_in(i) = '1' then
|
||||
v.irq := '1';
|
||||
v.xisr := std_ulogic_vector(to_unsigned(16 + i, 24));
|
||||
v.pending_priority := HW_PRIORITY; -- hardware HW IRQs
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
|
||||
-- Do mfrr as a higher priority so mfrr_pending is cleared
|
||||
if unsigned(r.mfrr) < unsigned(r.cppr) then --
|
||||
report "XICS: MFRR INTERRUPT";
|
||||
-- IPI
|
||||
if r.mfrr_pending = '1' then
|
||||
v.irq := '1';
|
||||
v.xisr := x"000002"; -- special XICS MFRR IRQ source number
|
||||
v.pending_priority := r.mfrr;
|
||||
v.mfrr_pending := '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Accept the interrupt
|
||||
if xirr_accept_rd = '1' then
|
||||
report "XICS: ACCEPT" &
|
||||
" cppr:" & to_hstring(r.cppr) &
|
||||
" xisr:" & to_hstring(r.xisr) &
|
||||
" mfrr:" & to_hstring(r.mfrr);
|
||||
v.cppr := r.pending_priority;
|
||||
end if;
|
||||
|
||||
if irq_eoi = '1' then
|
||||
v.irq := '0';
|
||||
end if;
|
||||
|
||||
if rst = '1' then
|
||||
v := reg_internal_init;
|
||||
end if;
|
||||
|
||||
r_next <= v;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture behaviour;
|
||||
Loading…
Reference in New Issue