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litesdcard: add lattice, regenerate

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Modifies litescard generate script to take a clock speed.

Regenerated verilog with latest litesdcard
e52c731 ("Bump year.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
fpu-constant
Matt Johnston 3 years ago
parent d794cc70b1
commit 42959184dd
3 changed files with 4899 additions and 557 deletions
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9
litesdcard/gen-src/generate.sh
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@ -1,6 +1,7 @@
#!/bin/bash

VENDORS="xilinx"
# vendor:sysclk
VENDORS="xilinx:100 lattice:48"

ME=$(realpath $0)
echo ME=$ME
@ -13,8 +14,10 @@ mkdir -p $BUILD_PATH
GEN_PATH=$PARENT_PATH/generated
mkdir -p $GEN_PATH

for i in $VENDORS
for i_clk in $VENDORS
do
i=$(echo $i_clk | cut -d : -f 1)
clk=$(echo $i_clk | cut -d : -f 2)
TARGET_BUILD_PATH=$BUILD_PATH/$i
TARGET_GEN_PATH=$GEN_PATH/$i
rm -rf $TARGET_BUILD_PATH
@ -23,7 +26,7 @@ do
mkdir -p $TARGET_GEN_PATH

echo "Generating $i in $TARGET_BUILD_PATH"
(cd $TARGET_BUILD_PATH && litesdcard_gen --vendor $i)
(cd $TARGET_BUILD_PATH && litesdcard_gen --vendor $i --clk-freq $clk)

cp $TARGET_BUILD_PATH/build/gateware/litesdcard_core.v $TARGET_GEN_PATH/
done

4288
litesdcard/generated/lattice/litesdcard_core.v
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137
litesdcard/generated/xilinx/litesdcard_core.v
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@ -1,7 +1,23 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (35203d6) & LiteX (79ac0931) on 2021-08-10 08:40:47
//--------------------------------------------------------------------------------
module litesdcard_core(
// -----------------------------------------------------------------------------
// Auto-Generated by: __ _ __ _ __
// / / (_) /____ | |/_/
// / /__/ / __/ -_)> <
// /____/_/\__/\__/_/|_|
// Build your hardware, easily!
// https://github.com/enjoy-digital/litex
//
// Filename : litesdcard_core.v
// Device :
// LiteX sha1 : --------
// Date : 2022-01-14 07:30:19
//------------------------------------------------------------------------------


//------------------------------------------------------------------------------
// Module
//------------------------------------------------------------------------------

module litesdcard_core (
input wire clk,
input wire rst,
input wire [29:0] wb_ctrl_adr,
@ -33,6 +49,11 @@ module litesdcard_core(
output wire irq
);


//------------------------------------------------------------------------------
// Signals
//------------------------------------------------------------------------------

wire sys_clk;
wire sys_rst;
wire por_clk;
@ -142,7 +163,7 @@ reg cmdr_source_ready = 1'd0;
reg cmdr_source_last = 1'd0;
reg [7:0] cmdr_source_payload_data = 8'd0;
reg [2:0] cmdr_source_payload_status = 3'd0;
reg [31:0] cmdr_timeout = 32'd100000000;
reg [31:0] cmdr_timeout = 32'd100;
reg [7:0] cmdr_count = 8'd0;
reg cmdr_busy = 1'd0;
wire cmdr_cmdr_pads_in_valid;
@ -306,7 +327,7 @@ reg datar_source_last = 1'd0;
reg [7:0] datar_source_payload_data = 8'd0;
reg [2:0] datar_source_payload_status = 3'd0;
reg datar_stop = 1'd0;
reg [31:0] datar_timeout = 32'd100000000;
reg [31:0] datar_timeout = 32'd100;
reg [9:0] datar_count = 10'd0;
wire datar_datar_pads_in_valid;
reg datar_datar_pads_in_ready = 1'd0;
@ -1110,6 +1131,10 @@ wire sdrio_clk_13;
wire sdrio_clk_14;
wire sdrio_clk_15;

//------------------------------------------------------------------------------
// Combinatorial Logic
//------------------------------------------------------------------------------

assign wb_ctrl_adr_1 = wb_ctrl_adr;
assign wb_ctrl_dat_w_1 = wb_ctrl_dat_w;
assign wb_ctrl_dat_r = wb_ctrl_dat_r_1;
@ -1411,7 +1436,7 @@ always @(*) begin
cmdr_sink_ready <= 1'd1;
if ((cmdr_sink_payload_cmd_type == 2'd3)) begin
cmdr_source_valid <= 1'd0;
cmdr_timeout_sdphycmdr_next_value0 <= 27'd100000000;
cmdr_timeout_sdphycmdr_next_value0 <= 7'd100;
cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1;
subfragments_sdphycmdr_next_state <= 2'd3;
end else begin
@ -1475,7 +1500,7 @@ always @(*) begin
end
end
default: begin
cmdr_timeout_sdphycmdr_next_value0 <= 27'd100000000;
cmdr_timeout_sdphycmdr_next_value0 <= 7'd100;
cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1;
cmdr_count_sdphycmdr_next_value1 <= 1'd0;
cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1;
@ -1762,7 +1787,7 @@ always @(*) begin
datar_count_sdphydatar_next_value_ce0 <= 1'd1;
if ((datar_sink_valid & datar_pads_out_ready)) begin
datar_pads_out_payload_clk <= 1'd1;
datar_timeout_sdphydatar_next_value1 <= 32'd100000000;
datar_timeout_sdphydatar_next_value1 <= 32'd100;
datar_timeout_sdphydatar_next_value_ce1 <= 1'd1;
datar_count_sdphydatar_next_value0 <= 1'd0;
datar_count_sdphydatar_next_value_ce0 <= 1'd1;
@ -2262,11 +2287,11 @@ always @(*) begin
end
assign sdblock2mem_start = (sdblock2mem_sink_sink_valid0 & sdblock2mem_sink_sink_first);
always @(*) begin
sdblock2mem_fifo_sink_first <= 1'd0;
sdblock2mem_fifo_sink_last <= 1'd0;
sdblock2mem_sink_sink_ready0 <= 1'd0;
sdblock2mem_fifo_sink_payload_data <= 8'd0;
sdblock2mem_fifo_sink_valid <= 1'd0;
sdblock2mem_fifo_sink_first <= 1'd0;
if ((sdblock2mem_wishbonedmawriter_enable_storage & (sdblock2mem_start | sdblock2mem_connect))) begin
sdblock2mem_fifo_sink_valid <= sdblock2mem_sink_sink_valid0;
sdblock2mem_sink_sink_ready0 <= sdblock2mem_fifo_sink_ready;
@ -2442,13 +2467,13 @@ always @(*) begin
endcase
end
always @(*) begin
subfragments_sdmem2blockdma_resetinserter_next_state <= 2'd0;
sdmem2block_dma_sink_last <= 1'd0;
sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value <= 32'd0;
sdmem2block_dma_sink_payload_address <= 32'd0;
sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce <= 1'd0;
sdmem2block_dma_done_status <= 1'd0;
sdmem2block_dma_sink_valid <= 1'd0;
subfragments_sdmem2blockdma_resetinserter_next_state <= 2'd0;
sdmem2block_dma_done_status <= 1'd0;
subfragments_sdmem2blockdma_resetinserter_next_state <= subfragments_sdmem2blockdma_resetinserter_state;
case (subfragments_sdmem2blockdma_resetinserter_state)
1'd1: begin
@ -2580,8 +2605,8 @@ always @(*) begin
litesdcardcore_next_state <= 1'd0;
litesdcardcore_litesdcardcore_adr <= 14'd0;
litesdcardcore_litesdcardcore_we <= 1'd0;
litesdcardcore_litesdcardcore_dat_w <= 32'd0;
litesdcardcore_litesdcardcore_wishbone_ack <= 1'd0;
litesdcardcore_litesdcardcore_dat_w <= 32'd0;
litesdcardcore_next_state <= litesdcardcore_state;
case (litesdcardcore_state)
1'd1: begin
@ -2638,8 +2663,8 @@ assign litesdcardcore_shared_err = wb_dma_err_1;
assign litesdcardcore_wait = ((litesdcardcore_shared_stb & litesdcardcore_shared_cyc) & (~litesdcardcore_shared_ack));
always @(*) begin
litesdcardcore_error <= 1'd0;
litesdcardcore_shared_dat_r <= 32'd0;
litesdcardcore_shared_ack <= 1'd0;
litesdcardcore_shared_dat_r <= 32'd0;
litesdcardcore_shared_ack <= wb_dma_ack_1;
litesdcardcore_shared_dat_r <= ({32{litesdcardcore_slave_sel_r}} & wb_dma_dat_r_1);
if (litesdcardcore_done) begin
@ -2661,8 +2686,8 @@ always @(*) begin
end
assign litesdcardcore_csrbank0_scratch0_r = litesdcardcore_interface0_bank_bus_dat_w[31:0];
always @(*) begin
litesdcardcore_csrbank0_scratch0_re <= 1'd0;
litesdcardcore_csrbank0_scratch0_we <= 1'd0;
litesdcardcore_csrbank0_scratch0_re <= 1'd0;
if ((litesdcardcore_csrbank0_sel & (litesdcardcore_interface0_bank_bus_adr[8:0] == 1'd1))) begin
litesdcardcore_csrbank0_scratch0_re <= litesdcardcore_interface0_bank_bus_we;
litesdcardcore_csrbank0_scratch0_we <= (~litesdcardcore_interface0_bank_bus_we);
@ -2700,8 +2725,8 @@ always @(*) begin
end
assign litesdcardcore_csrbank1_dma_base0_r = litesdcardcore_interface1_bank_bus_dat_w[31:0];
always @(*) begin
litesdcardcore_csrbank1_dma_base0_we <= 1'd0;
litesdcardcore_csrbank1_dma_base0_re <= 1'd0;
litesdcardcore_csrbank1_dma_base0_we <= 1'd0;
if ((litesdcardcore_csrbank1_sel & (litesdcardcore_interface1_bank_bus_adr[8:0] == 1'd1))) begin
litesdcardcore_csrbank1_dma_base0_re <= litesdcardcore_interface1_bank_bus_we;
litesdcardcore_csrbank1_dma_base0_we <= (~litesdcardcore_interface1_bank_bus_we);
@ -2764,8 +2789,8 @@ assign sdblock2mem_wishbonedmawriter_offset_we = litesdcardcore_csrbank1_dma_off
assign litesdcardcore_csrbank2_sel = (litesdcardcore_interface2_bank_bus_adr[13:9] == 2'd2);
assign litesdcardcore_csrbank2_cmd_argument0_r = litesdcardcore_interface2_bank_bus_dat_w[31:0];
always @(*) begin
litesdcardcore_csrbank2_cmd_argument0_we <= 1'd0;
litesdcardcore_csrbank2_cmd_argument0_re <= 1'd0;
litesdcardcore_csrbank2_cmd_argument0_we <= 1'd0;
if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 1'd0))) begin
litesdcardcore_csrbank2_cmd_argument0_re <= litesdcardcore_interface2_bank_bus_we;
litesdcardcore_csrbank2_cmd_argument0_we <= (~litesdcardcore_interface2_bank_bus_we);
@ -2854,8 +2879,8 @@ always @(*) begin
end
assign litesdcardcore_csrbank2_block_count0_r = litesdcardcore_interface2_bank_bus_dat_w[31:0];
always @(*) begin
litesdcardcore_csrbank2_block_count0_we <= 1'd0;
litesdcardcore_csrbank2_block_count0_re <= 1'd0;
litesdcardcore_csrbank2_block_count0_we <= 1'd0;
if ((litesdcardcore_csrbank2_sel & (litesdcardcore_interface2_bank_bus_adr[8:0] == 4'd10))) begin
litesdcardcore_csrbank2_block_count0_re <= litesdcardcore_interface2_bank_bus_we;
litesdcardcore_csrbank2_block_count0_we <= (~litesdcardcore_interface2_bank_bus_we);
@ -2913,8 +2938,8 @@ always @(*) begin
end
assign litesdcardcore_csrbank3_enable0_r = litesdcardcore_interface3_bank_bus_dat_w[3:0];
always @(*) begin
litesdcardcore_csrbank3_enable0_re <= 1'd0;
litesdcardcore_csrbank3_enable0_we <= 1'd0;
litesdcardcore_csrbank3_enable0_re <= 1'd0;
if ((litesdcardcore_csrbank3_sel & (litesdcardcore_interface3_bank_bus_adr[8:0] == 2'd2))) begin
litesdcardcore_csrbank3_enable0_re <= litesdcardcore_interface3_bank_bus_we;
litesdcardcore_csrbank3_enable0_we <= (~litesdcardcore_interface3_bank_bus_we);
@ -2973,8 +2998,8 @@ always @(*) begin
end
assign litesdcardcore_csrbank4_dma_enable0_r = litesdcardcore_interface4_bank_bus_dat_w[0];
always @(*) begin
litesdcardcore_csrbank4_dma_enable0_re <= 1'd0;
litesdcardcore_csrbank4_dma_enable0_we <= 1'd0;
litesdcardcore_csrbank4_dma_enable0_re <= 1'd0;
if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 2'd3))) begin
litesdcardcore_csrbank4_dma_enable0_re <= litesdcardcore_interface4_bank_bus_we;
litesdcardcore_csrbank4_dma_enable0_we <= (~litesdcardcore_interface4_bank_bus_we);
@ -3000,8 +3025,8 @@ always @(*) begin
end
assign litesdcardcore_csrbank4_dma_offset_r = litesdcardcore_interface4_bank_bus_dat_w[31:0];
always @(*) begin
litesdcardcore_csrbank4_dma_offset_re <= 1'd0;
litesdcardcore_csrbank4_dma_offset_we <= 1'd0;
litesdcardcore_csrbank4_dma_offset_re <= 1'd0;
if ((litesdcardcore_csrbank4_sel & (litesdcardcore_interface4_bank_bus_adr[8:0] == 3'd6))) begin
litesdcardcore_csrbank4_dma_offset_re <= litesdcardcore_interface4_bank_bus_we;
litesdcardcore_csrbank4_dma_offset_we <= (~litesdcardcore_interface4_bank_bus_we);
@ -3028,8 +3053,8 @@ always @(*) begin
end
assign litesdcardcore_csrbank5_clocker_divider0_r = litesdcardcore_interface5_bank_bus_dat_w[8:0];
always @(*) begin
litesdcardcore_csrbank5_clocker_divider0_we <= 1'd0;
litesdcardcore_csrbank5_clocker_divider0_re <= 1'd0;
litesdcardcore_csrbank5_clocker_divider0_we <= 1'd0;
if ((litesdcardcore_csrbank5_sel & (litesdcardcore_interface5_bank_bus_adr[8:0] == 1'd1))) begin
litesdcardcore_csrbank5_clocker_divider0_re <= litesdcardcore_interface5_bank_bus_we;
litesdcardcore_csrbank5_clocker_divider0_we <= (~litesdcardcore_interface5_bank_bus_we);
@ -3192,6 +3217,11 @@ assign sdrio_clk_13 = sys_clk;
assign sdrio_clk_14 = sys_clk;
assign sdrio_clk_15 = sys_clk;


//------------------------------------------------------------------------------
// Synchronous Logic
//------------------------------------------------------------------------------

always @(posedge por_clk) begin
int_rst <= rst;
end
@ -3981,7 +4011,7 @@ always @(posedge sys_clk) begin
clocker_ce_delayed <= 1'd0;
init_count <= 8'd0;
cmdw_count <= 8'd0;
cmdr_timeout <= 32'd100000000;
cmdr_timeout <= 32'd100;
cmdr_count <= 8'd0;
cmdr_busy <= 1'd0;
cmdr_cmdr_run <= 1'd0;
@ -4004,7 +4034,7 @@ always @(posedge sys_clk) begin
dataw_crc_converter_strobe_all <= 1'd0;
dataw_crc_buf_source_valid <= 1'd0;
dataw_crc_buf_source_payload_data <= 8'd0;
datar_timeout <= 32'd100000000;
datar_timeout <= 32'd100;
datar_count <= 10'd0;
datar_datar_run <= 1'd0;
datar_datar_converter_source_payload_data <= 8'd0;
@ -4116,53 +4146,70 @@ always @(posedge sys_clk) begin
end
end


//------------------------------------------------------------------------------
// Specialized Logic
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Memory storage: 8-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Async | Write: ---- |
reg [9:0] storage[0:7];
reg [9:0] memdat;
reg [9:0] storage_dat0;
always @(posedge sys_clk) begin
if (sdcore_fifo_wrport_we)
storage[sdcore_fifo_wrport_adr] <= sdcore_fifo_wrport_dat_w;
memdat <= storage[sdcore_fifo_wrport_adr];
storage_dat0 <= storage[sdcore_fifo_wrport_adr];
end

always @(posedge sys_clk) begin
end

assign sdcore_fifo_wrport_dat_r = memdat;
assign sdcore_fifo_wrport_dat_r = storage_dat0;
assign sdcore_fifo_rdport_dat_r = storage[sdcore_fifo_rdport_adr];


//------------------------------------------------------------------------------
// Memory storage_1: 512-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage_1[0:511];
reg [9:0] memdat_1;
reg [9:0] memdat_2;
reg [9:0] storage_1_dat0;
reg [9:0] storage_1_dat1;
always @(posedge sys_clk) begin
if (sdblock2mem_fifo_wrport_we)
storage_1[sdblock2mem_fifo_wrport_adr] <= sdblock2mem_fifo_wrport_dat_w;
memdat_1 <= storage_1[sdblock2mem_fifo_wrport_adr];
storage_1_dat0 <= storage_1[sdblock2mem_fifo_wrport_adr];
end

always @(posedge sys_clk) begin
if (sdblock2mem_fifo_rdport_re)
memdat_2 <= storage_1[sdblock2mem_fifo_rdport_adr];
storage_1_dat1 <= storage_1[sdblock2mem_fifo_rdport_adr];
end
assign sdblock2mem_fifo_wrport_dat_r = storage_1_dat0;
assign sdblock2mem_fifo_rdport_dat_r = storage_1_dat1;

assign sdblock2mem_fifo_wrport_dat_r = memdat_1;
assign sdblock2mem_fifo_rdport_dat_r = memdat_2;

//------------------------------------------------------------------------------
// Memory storage_2: 512-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10
// Port 1 | Read: Sync | Write: ---- |
reg [9:0] storage_2[0:511];
reg [9:0] memdat_3;
reg [9:0] memdat_4;
reg [9:0] storage_2_dat0;
reg [9:0] storage_2_dat1;
always @(posedge sys_clk) begin
if (sdmem2block_fifo_wrport_we)
storage_2[sdmem2block_fifo_wrport_adr] <= sdmem2block_fifo_wrport_dat_w;
memdat_3 <= storage_2[sdmem2block_fifo_wrport_adr];
storage_2_dat0 <= storage_2[sdmem2block_fifo_wrport_adr];
end

always @(posedge sys_clk) begin
if (sdmem2block_fifo_rdport_re)
memdat_4 <= storage_2[sdmem2block_fifo_rdport_adr];
storage_2_dat1 <= storage_2[sdmem2block_fifo_rdport_adr];
end
assign sdmem2block_fifo_wrport_dat_r = storage_2_dat0;
assign sdmem2block_fifo_rdport_dat_r = storage_2_dat1;

assign sdmem2block_fifo_wrport_dat_r = memdat_3;
assign sdmem2block_fifo_rdport_dat_r = memdat_4;

IOBUF IOBUF(
.I(xilinxsdrtristateimpl0__o),
@ -4200,3 +4247,7 @@ IOBUF IOBUF_4(
);

endmodule

// -----------------------------------------------------------------------------
// Auto-Generated by LiteX on 2022-01-14 07:30:20.
//------------------------------------------------------------------------------

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