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microwatt
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Add ram file to synthesis build dependencies

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Signed-off-by: Michael Neuling <mikey@neuling.org>
jtag-port
Michael Neuling 4 years ago
parent 7347786b08
commit 45fd2354f2
1 changed files with 2 additions and 2 deletions
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4
Makefile
Unescape Escape View File

@ -175,10 +175,10 @@ fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \


synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)


microwatt.json: $(synth_files) microwatt.json: $(synth_files) $(RAM_INIT_FILE)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@" $(uart_files) $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@" $(uart_files)


microwatt.v: $(synth_files) microwatt.v: $(synth_files) $(RAM_INIT_FILE)
$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" $(uart_files) $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" $(uart_files)


# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall

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