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Merge pull request #64 from antonblanchard/reformat-3

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Reformat some more files
jtag-port
Anton Blanchard 5 years ago committed by GitHub
parent 48f4dcece8 df1165bdfc
commit 4df05e0598
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GPG Key ID: 4AEE18F83AFDEB23
12 changed files with 722 additions and 714 deletions
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90
cr_file.vhdl
Unescape Escape View File

@ -6,55 +6,55 @@ library work;
use work.common.all; use work.common.all;


entity cr_file is entity cr_file is
port( port(
clk : in std_logic; clk : in std_logic;


d_in : in Decode2ToCrFileType; d_in : in Decode2ToCrFileType;
d_out : out CrFileToDecode2Type; d_out : out CrFileToDecode2Type;


w_in : in WritebackToCrFileType w_in : in WritebackToCrFileType
); );
end entity cr_file; end entity cr_file;


architecture behaviour of cr_file is architecture behaviour of cr_file is
signal crs : std_ulogic_vector(31 downto 0) := (others => '0'); signal crs : std_ulogic_vector(31 downto 0) := (others => '0');
signal crs_updated : std_ulogic_vector(31 downto 0) := (others => '0'); signal crs_updated : std_ulogic_vector(31 downto 0) := (others => '0');
begin begin
cr_create_0: process(all) cr_create_0: process(all)
variable hi, lo : integer := 0; variable hi, lo : integer := 0;
variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0'); variable cr_tmp : std_ulogic_vector(31 downto 0) := (others => '0');
begin begin
cr_tmp := crs; cr_tmp := crs;


for i in 0 to 7 loop for i in 0 to 7 loop
if w_in.write_cr_mask(i) = '1' then if w_in.write_cr_mask(i) = '1' then
lo := i*4; lo := i*4;
hi := lo + 3; hi := lo + 3;
cr_tmp(hi downto lo) := w_in.write_cr_data(hi downto lo); cr_tmp(hi downto lo) := w_in.write_cr_data(hi downto lo);
end if; end if;
end loop; end loop;


crs_updated <= cr_tmp; crs_updated <= cr_tmp;
end process; end process;


-- synchronous writes -- synchronous writes
cr_write_0: process(clk) cr_write_0: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if w_in.write_cr_enable = '1' then if w_in.write_cr_enable = '1' then
report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask); report "Writing " & to_hstring(w_in.write_cr_data) & " to CR mask " & to_hstring(w_in.write_cr_mask);
end if; end if;
crs <= crs_updated; crs <= crs_updated;
end if; end if;
end process; end process;


-- asynchronous reads -- asynchronous reads
cr_read_0: process(all) cr_read_0: process(all)
begin begin
-- just return the entire CR to make mfcrf easier for now -- just return the entire CR to make mfcrf easier for now
if d_in.read = '1' then if d_in.read = '1' then
report "Reading CR " & to_hstring(crs_updated); report "Reading CR " & to_hstring(crs_updated);
end if; end if;
d_out.read_cr_data <= crs_updated; d_out.read_cr_data <= crs_updated;
end process; end process;
end architecture behaviour; end architecture behaviour;

76
execute2.vhdl
Unescape Escape View File

@ -11,47 +11,47 @@ use work.ppc_fx_insns.all;
-- We handle rc form instructions here -- We handle rc form instructions here


entity execute2 is entity execute2 is
port ( port (
clk : in std_ulogic; clk : in std_ulogic;


e_in : in Execute1ToExecute2Type; e_in : in Execute1ToExecute2Type;
e_out : out Execute2ToWritebackType e_out : out Execute2ToWritebackType
); );
end execute2; end execute2;


architecture behave of execute2 is architecture behave of execute2 is
signal r, rin : Execute2ToWritebackType; signal r, rin : Execute2ToWritebackType;
begin begin
execute2_0: process(clk) execute2_0: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
r <= rin; r <= rin;
end if; end if;
end process; end process;


execute2_1: process(all) execute2_1: process(all)
variable v : Execute2ToWritebackType; variable v : Execute2ToWritebackType;
begin begin
v := rin; v := rin;


v.valid := e_in.valid; v.valid := e_in.valid;
v.write_enable := e_in.write_enable; v.write_enable := e_in.write_enable;
v.write_reg := e_in.write_reg; v.write_reg := e_in.write_reg;
v.write_data := e_in.write_data; v.write_data := e_in.write_data;
v.write_cr_enable := e_in.write_cr_enable; v.write_cr_enable := e_in.write_cr_enable;
v.write_cr_mask := e_in.write_cr_mask; v.write_cr_mask := e_in.write_cr_mask;
v.write_cr_data := e_in.write_cr_data; v.write_cr_data := e_in.write_cr_data;


if e_in.valid = '1' and e_in.rc = '1' then if e_in.valid = '1' and e_in.rc = '1' then
v.write_cr_enable := '1'; v.write_cr_enable := '1';
v.write_cr_mask := num_to_fxm(0); v.write_cr_mask := num_to_fxm(0);
v.write_cr_data := ppc_cmpi('1', e_in.write_data, x"0000") & x"0000000"; v.write_cr_data := ppc_cmpi('1', e_in.write_data, x"0000") & x"0000000";
end if; end if;


-- Update registers -- Update registers
rin <= v; rin <= v;


-- Update outputs -- Update outputs
e_out <= r; e_out <= r;
end process; end process;
end; end;

46
glibc_random.vhdl
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@ -6,33 +6,33 @@ library work;
use work.glibc_random_helpers.all; use work.glibc_random_helpers.all;


package glibc_random is package glibc_random is
function pseudorand(a: integer) return std_ulogic_vector; function pseudorand(a: integer) return std_ulogic_vector;
function pseudorand1 return std_ulogic; function pseudorand1 return std_ulogic;
end package glibc_random; end package glibc_random;


package body glibc_random is package body glibc_random is
function pseudorand(a: integer) return std_ulogic_vector is function pseudorand(a: integer) return std_ulogic_vector is
variable tmp1, tmp2, tmp3, tmp4: std_ulogic_vector(31 downto 0); variable tmp1, tmp2, tmp3, tmp4: std_ulogic_vector(31 downto 0);
variable ret: std_ulogic_vector(63 downto 0); variable ret: std_ulogic_vector(63 downto 0);
begin begin
tmp1 := std_ulogic_vector(to_unsigned(random, 32)); tmp1 := std_ulogic_vector(to_unsigned(random, 32));
tmp2 := std_ulogic_vector(to_unsigned(random, 32)); tmp2 := std_ulogic_vector(to_unsigned(random, 32));
if a <= 32 then if a <= 32 then
ret := tmp1 & tmp2; ret := tmp1 & tmp2;
else else
tmp3 := std_ulogic_vector(to_unsigned(random, 32)); tmp3 := std_ulogic_vector(to_unsigned(random, 32));
tmp4 := std_ulogic_vector(to_unsigned(random, 32)); tmp4 := std_ulogic_vector(to_unsigned(random, 32));


ret := tmp1(15 downto 0) & tmp2(15 downto 0) & tmp3(15 downto 0) & tmp4(15 downto 0); ret := tmp1(15 downto 0) & tmp2(15 downto 0) & tmp3(15 downto 0) & tmp4(15 downto 0);
end if; end if;


return ret((a-1) downto 0); return ret((a-1) downto 0);
end; end;


function pseudorand1 return std_ulogic is function pseudorand1 return std_ulogic is
variable tmp: std_ulogic_vector(31 downto 0); variable tmp: std_ulogic_vector(31 downto 0);
begin begin
tmp := std_ulogic_vector(to_unsigned(random, 32)); tmp := std_ulogic_vector(to_unsigned(random, 32));
return tmp(0); return tmp(0);
end; end;
end package body glibc_random; end package body glibc_random;

24
glibc_random_helpers.vhdl
Unescape Escape View File

@ -1,19 +1,19 @@
package glibc_random_helpers is package glibc_random_helpers is
procedure srand (v : integer); procedure srand (v : integer);
attribute foreign of srand : procedure is "VHPIDIRECT srand"; attribute foreign of srand : procedure is "VHPIDIRECT srand";


function random return integer; function random return integer;
attribute foreign of random : function is "VHPIDIRECT random"; attribute foreign of random : function is "VHPIDIRECT random";
end glibc_random_helpers; end glibc_random_helpers;


package body glibc_random_helpers is package body glibc_random_helpers is
procedure srand (v : integer) is procedure srand (v : integer) is
begin begin
assert false severity failure; assert false severity failure;
end srand; end srand;


function random return integer is function random return integer is
begin begin
assert false severity failure; assert false severity failure;
end random; end random;
end glibc_random_helpers; end glibc_random_helpers;

350
multiply_tb.vhdl
Unescape Escape View File

@ -12,252 +12,252 @@ entity multiply_tb is
end multiply_tb; end multiply_tb;


architecture behave of multiply_tb is architecture behave of multiply_tb is
signal clk : std_ulogic; signal clk : std_ulogic;
constant clk_period : time := 10 ns; constant clk_period : time := 10 ns;


constant pipeline_depth: integer := 4; constant pipeline_depth : integer := 4;


signal m1 : Decode2ToMultiplyType; signal m1 : Decode2ToMultiplyType;
signal m2 : MultiplyToWritebackType; signal m2 : MultiplyToWritebackType;
begin begin
multiply_0: entity work.multiply multiply_0: entity work.multiply
generic map (PIPELINE_DEPTH => pipeline_depth) generic map (PIPELINE_DEPTH => pipeline_depth)
port map (clk => clk, m_in => m1, m_out => m2); port map (clk => clk, m_in => m1, m_out => m2);


clk_process: process clk_process: process
begin begin
clk <= '0'; clk <= '0';
wait for clk_period/2; wait for clk_period/2;
clk <= '1'; clk <= '1';
wait for clk_period/2; wait for clk_period/2;
end process; end process;


stim_process: process stim_process: process
variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0); variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
variable si: std_ulogic_vector(15 downto 0); variable si: std_ulogic_vector(15 downto 0);
begin begin
wait for clk_period; wait for clk_period;


m1.valid <= '1'; m1.valid <= '1';
m1.insn_type <= OP_MUL_L64; m1.insn_type <= OP_MUL_L64;
m1.write_reg <= "10001"; m1.write_reg <= "10001";
m1.data1 <= '0' & x"0000000000001000"; m1.data1 <= '0' & x"0000000000001000";
m1.data2 <= '0' & x"0000000000001111"; m1.data2 <= '0' & x"0000000000001111";
m1.rc <= '0'; m1.rc <= '0';


wait for clk_period; wait for clk_period;
assert m2.valid = '0'; assert m2.valid = '0';


m1.valid <= '0'; m1.valid <= '0';


wait for clk_period; wait for clk_period;
assert m2.valid = '0'; assert m2.valid = '0';


wait for clk_period; wait for clk_period;
assert m2.valid = '0'; assert m2.valid = '0';


wait for clk_period; wait for clk_period;
assert m2.valid = '1'; assert m2.valid = '1';
assert m2.write_reg_enable = '1'; assert m2.write_reg_enable = '1';
assert m2.write_reg_nr = "10001"; assert m2.write_reg_nr = "10001";
assert m2.write_reg_data = x"0000000001111000"; assert m2.write_reg_data = x"0000000001111000";
assert m2.write_cr_enable = '0'; assert m2.write_cr_enable = '0';


wait for clk_period; wait for clk_period;
assert m2.valid = '0'; assert m2.valid = '0';


m1.valid <= '1'; m1.valid <= '1';
m1.rc <= '1'; m1.rc <= '1';


wait for clk_period; wait for clk_period;
assert m2.valid = '0'; assert m2.valid = '0';


m1.valid <= '0'; m1.valid <= '0';


wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);
assert m2.valid = '1'; assert m2.valid = '1';
assert m2.write_reg_enable = '1'; assert m2.write_reg_enable = '1';
assert m2.write_reg_nr = "10001"; assert m2.write_reg_nr = "10001";
assert m2.write_reg_data = x"0000000001111000"; assert m2.write_reg_data = x"0000000001111000";
assert m2.write_cr_enable = '1'; assert m2.write_cr_enable = '1';
assert m2.write_cr_data = x"40000000"; assert m2.write_cr_data = x"40000000";


-- test mulld -- test mulld
mulld_loop : for i in 0 to 1000 loop mulld_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := pseudorand(ra'length);
rb := pseudorand(rb'length); rb := pseudorand(rb'length);


behave_rt := ppc_mulld(ra, rb); behave_rt := ppc_mulld(ra, rb);


m1.data1 <= '0' & ra; m1.data1 <= '0' & ra;
m1.data2 <= '0' & rb; m1.data2 <= '0' & rb;
m1.valid <= '1'; m1.valid <= '1';
m1.insn_type <= OP_MUL_L64; m1.insn_type <= OP_MUL_L64;


wait for clk_period; wait for clk_period;


m1.valid <= '0'; m1.valid <= '0';


wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);


assert m2.valid = '1'; assert m2.valid = '1';


assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data) assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data); report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop; end loop;


-- test mulhdu -- test mulhdu
mulhdu_loop : for i in 0 to 1000 loop mulhdu_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := pseudorand(ra'length);
rb := pseudorand(rb'length); rb := pseudorand(rb'length);


behave_rt := ppc_mulhdu(ra, rb); behave_rt := ppc_mulhdu(ra, rb);


m1.data1 <= '0' & ra; m1.data1 <= '0' & ra;
m1.data2 <= '0' & rb; m1.data2 <= '0' & rb;
m1.valid <= '1'; m1.valid <= '1';
m1.insn_type <= OP_MUL_H64; m1.insn_type <= OP_MUL_H64;


wait for clk_period; wait for clk_period;


m1.valid <= '0'; m1.valid <= '0';


wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);


assert m2.valid = '1'; assert m2.valid = '1';


assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data) assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data); report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop; end loop;


-- test mulhd -- test mulhd
mulhd_loop : for i in 0 to 1000 loop mulhd_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := pseudorand(ra'length);
rb := pseudorand(rb'length); rb := pseudorand(rb'length);


behave_rt := ppc_mulhd(ra, rb); behave_rt := ppc_mulhd(ra, rb);


m1.data1 <= ra(63) & ra; m1.data1 <= ra(63) & ra;
m1.data2 <= rb(63) & rb; m1.data2 <= rb(63) & rb;
m1.valid <= '1'; m1.valid <= '1';
m1.insn_type <= OP_MUL_H64; m1.insn_type <= OP_MUL_H64;


wait for clk_period; wait for clk_period;


m1.valid <= '0'; m1.valid <= '0';


wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);


assert m2.valid = '1'; assert m2.valid = '1';


assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data) assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data); report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop; end loop;


-- test mullw -- test mullw
mullw_loop : for i in 0 to 1000 loop mullw_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := pseudorand(ra'length);
rb := pseudorand(rb'length); rb := pseudorand(rb'length);


behave_rt := ppc_mullw(ra, rb); behave_rt := ppc_mullw(ra, rb);


m1.data1 <= (others => ra(31)); m1.data1 <= (others => ra(31));
m1.data1(31 downto 0) <= ra(31 downto 0); m1.data1(31 downto 0) <= ra(31 downto 0);
m1.data2 <= (others => rb(31)); m1.data2 <= (others => rb(31));
m1.data2(31 downto 0) <= rb(31 downto 0); m1.data2(31 downto 0) <= rb(31 downto 0);
m1.valid <= '1'; m1.valid <= '1';
m1.insn_type <= OP_MUL_L64; m1.insn_type <= OP_MUL_L64;


wait for clk_period; wait for clk_period;


m1.valid <= '0'; m1.valid <= '0';


wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);


assert m2.valid = '1'; assert m2.valid = '1';


assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data) assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data); report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop; end loop;


-- test mulhw -- test mulhw
mulhw_loop : for i in 0 to 1000 loop mulhw_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := pseudorand(ra'length);
rb := pseudorand(rb'length); rb := pseudorand(rb'length);


behave_rt := ppc_mulhw(ra, rb); behave_rt := ppc_mulhw(ra, rb);


m1.data1 <= (others => ra(31)); m1.data1 <= (others => ra(31));
m1.data1(31 downto 0) <= ra(31 downto 0); m1.data1(31 downto 0) <= ra(31 downto 0);
m1.data2 <= (others => rb(31)); m1.data2 <= (others => rb(31));
m1.data2(31 downto 0) <= rb(31 downto 0); m1.data2(31 downto 0) <= rb(31 downto 0);
m1.valid <= '1'; m1.valid <= '1';
m1.insn_type <= OP_MUL_H32; m1.insn_type <= OP_MUL_H32;


wait for clk_period; wait for clk_period;


m1.valid <= '0'; m1.valid <= '0';


wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);


assert m2.valid = '1'; assert m2.valid = '1';


assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data) assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulhw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data); report "bad mulhw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop; end loop;


-- test mulhwu -- test mulhwu
mulhwu_loop : for i in 0 to 1000 loop mulhwu_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := pseudorand(ra'length);
rb := pseudorand(rb'length); rb := pseudorand(rb'length);


behave_rt := ppc_mulhwu(ra, rb); behave_rt := ppc_mulhwu(ra, rb);


m1.data1 <= (others => '0'); m1.data1 <= (others => '0');
m1.data1(31 downto 0) <= ra(31 downto 0); m1.data1(31 downto 0) <= ra(31 downto 0);
m1.data2 <= (others => '0'); m1.data2 <= (others => '0');
m1.data2(31 downto 0) <= rb(31 downto 0); m1.data2(31 downto 0) <= rb(31 downto 0);
m1.valid <= '1'; m1.valid <= '1';
m1.insn_type <= OP_MUL_H32; m1.insn_type <= OP_MUL_H32;


wait for clk_period; wait for clk_period;


m1.valid <= '0'; m1.valid <= '0';


wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);


assert m2.valid = '1'; assert m2.valid = '1';


assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data) assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulhwu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data); report "bad mulhwu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop; end loop;


-- test mulli -- test mulli
mulli_loop : for i in 0 to 1000 loop mulli_loop : for i in 0 to 1000 loop
ra := pseudorand(ra'length); ra := pseudorand(ra'length);
si := pseudorand(si'length); si := pseudorand(si'length);


behave_rt := ppc_mulli(ra, si); behave_rt := ppc_mulli(ra, si);


m1.data1 <= ra(63) & ra; m1.data1 <= ra(63) & ra;
m1.data2 <= (others => si(15)); m1.data2 <= (others => si(15));
m1.data2(15 downto 0) <= si; m1.data2(15 downto 0) <= si;
m1.valid <= '1'; m1.valid <= '1';
m1.insn_type <= OP_MUL_L64; m1.insn_type <= OP_MUL_L64;


wait for clk_period; wait for clk_period;


m1.valid <= '0'; m1.valid <= '0';


wait for clk_period * (pipeline_depth-1); wait for clk_period * (pipeline_depth-1);


assert m2.valid = '1'; assert m2.valid = '1';


assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data) assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data); report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop; end loop;


assert false report "end of test" severity failure; assert false report "end of test" severity failure;
wait; wait;
end process; end process;
end behave; end behave;

100
register_file.vhdl
Unescape Escape View File

@ -6,64 +6,64 @@ library work;
use work.common.all; use work.common.all;


entity register_file is entity register_file is
port( port(
clk : in std_logic; clk : in std_logic;


d_in : in Decode2ToRegisterFileType; d_in : in Decode2ToRegisterFileType;
d_out : out RegisterFileToDecode2Type; d_out : out RegisterFileToDecode2Type;


w_in : in WritebackToRegisterFileType; w_in : in WritebackToRegisterFileType;


-- debug -- debug
registers_out : out regfile registers_out : out regfile
); );
end entity register_file; end entity register_file;


architecture behaviour of register_file is architecture behaviour of register_file is
signal registers : regfile := (others => (others => '0')); signal registers : regfile := (others => (others => '0'));
begin begin
-- synchronous writes -- synchronous writes
register_write_0: process(clk) register_write_0: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if w_in.write_enable = '1' then if w_in.write_enable = '1' then
assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure; assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data); report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data; registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
end if; end if;
end if; end if;
end process register_write_0; end process register_write_0;


-- asynchronous reads -- asynchronous reads
register_read_0: process(all) register_read_0: process(all)
begin begin
if d_in.read1_enable = '1' then if d_in.read1_enable = '1' then
report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg)))); report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
end if; end if;
if d_in.read2_enable = '1' then if d_in.read2_enable = '1' then
report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg)))); report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
end if; end if;
if d_in.read3_enable = '1' then if d_in.read3_enable = '1' then
report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg)))); report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
end if; end if;
d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg))); d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg))); d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg)));
d_out.read3_data <= registers(to_integer(unsigned(d_in.read3_reg))); d_out.read3_data <= registers(to_integer(unsigned(d_in.read3_reg)));


-- Forward any written data -- Forward any written data
if w_in.write_enable = '1' then if w_in.write_enable = '1' then
if d_in.read1_reg = w_in.write_reg then if d_in.read1_reg = w_in.write_reg then
d_out.read1_data <= w_in.write_data; d_out.read1_data <= w_in.write_data;
end if; end if;
if d_in.read2_reg = w_in.write_reg then if d_in.read2_reg = w_in.write_reg then
d_out.read2_data <= w_in.write_data; d_out.read2_data <= w_in.write_data;
end if; end if;
if d_in.read3_reg = w_in.write_reg then if d_in.read3_reg = w_in.write_reg then
d_out.read3_data <= w_in.write_data; d_out.read3_data <= w_in.write_data;
end if; end if;
end if; end if;
end process register_read_0; end process register_read_0;


-- debug -- debug
registers_out <= registers; registers_out <= registers;
end architecture behaviour; end architecture behaviour;

36
sim_console.vhdl
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@ -2,29 +2,29 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;


package sim_console is package sim_console is
procedure sim_console_read (val: out std_ulogic_vector(63 downto 0)); procedure sim_console_read (val: out std_ulogic_vector(63 downto 0));
attribute foreign of sim_console_read : procedure is "VHPIDIRECT sim_console_read"; attribute foreign of sim_console_read : procedure is "VHPIDIRECT sim_console_read";


procedure sim_console_poll (val: out std_ulogic_vector(63 downto 0)); procedure sim_console_poll (val: out std_ulogic_vector(63 downto 0));
attribute foreign of sim_console_poll : procedure is "VHPIDIRECT sim_console_poll"; attribute foreign of sim_console_poll : procedure is "VHPIDIRECT sim_console_poll";


procedure sim_console_write (val: std_ulogic_vector(63 downto 0)); procedure sim_console_write (val: std_ulogic_vector(63 downto 0));
attribute foreign of sim_console_write : procedure is "VHPIDIRECT sim_console_write"; attribute foreign of sim_console_write : procedure is "VHPIDIRECT sim_console_write";
end sim_console; end sim_console;


package body sim_console is package body sim_console is
procedure sim_console_read (val: out std_ulogic_vector(63 downto 0)) is procedure sim_console_read (val: out std_ulogic_vector(63 downto 0)) is
begin begin
assert false report "VHPI" severity failure; assert false report "VHPI" severity failure;
end sim_console_read; end sim_console_read;


procedure sim_console_poll (val: out std_ulogic_vector(63 downto 0)) is procedure sim_console_poll (val: out std_ulogic_vector(63 downto 0)) is
begin begin
assert false report "VHPI" severity failure; assert false report "VHPI" severity failure;
end sim_console_poll; end sim_console_poll;


procedure sim_console_write (val: std_ulogic_vector(63 downto 0)) is procedure sim_console_write (val: std_ulogic_vector(63 downto 0)) is
begin begin
assert false report "VHPI" severity failure; assert false report "VHPI" severity failure;
end sim_console_write; end sim_console_write;
end sim_console; end sim_console;

114
simple_ram_behavioural.vhdl
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@ -8,70 +8,70 @@ use work.wishbone_types.all;
use work.simple_ram_behavioural_helpers.all; use work.simple_ram_behavioural_helpers.all;


entity mw_soc_memory is entity mw_soc_memory is
generic ( generic (
RAM_INIT_FILE : string; RAM_INIT_FILE : string;
MEMORY_SIZE : integer MEMORY_SIZE : integer
); );


port ( port (
clk : in std_ulogic; clk : in std_ulogic;
rst : in std_ulogic; rst : in std_ulogic;


wishbone_in : in wishbone_master_out; wishbone_in : in wishbone_master_out;
wishbone_out : out wishbone_slave_out wishbone_out : out wishbone_slave_out
); );
end mw_soc_memory; end mw_soc_memory;


architecture behave of mw_soc_memory is architecture behave of mw_soc_memory is
type wishbone_state_t is (IDLE, ACK); type wishbone_state_t is (IDLE, ACK);


signal state : wishbone_state_t := IDLE; signal state : wishbone_state_t := IDLE;
signal ret_ack : std_ulogic := '0'; signal ret_ack : std_ulogic := '0';
signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE, size => MEMORY_SIZE); signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE, size => MEMORY_SIZE);
signal reload : integer := 0; signal reload : integer := 0;
begin begin
wishbone_process: process(clk) wishbone_process: process(clk)
variable ret_dat: std_ulogic_vector(63 downto 0) := (others => '0'); variable ret_dat: std_ulogic_vector(63 downto 0) := (others => '0');
begin begin
wishbone_out.ack <= ret_ack and wishbone_in.cyc and wishbone_in.stb; wishbone_out.ack <= ret_ack and wishbone_in.cyc and wishbone_in.stb;
wishbone_out.dat <= ret_dat; wishbone_out.dat <= ret_dat;


if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
state <= IDLE; state <= IDLE;
ret_ack <= '0'; ret_ack <= '0';
else else
ret_dat := x"FFFFFFFFFFFFFFFF"; ret_dat := x"FFFFFFFFFFFFFFFF";


-- Active -- Active
if wishbone_in.cyc = '1' then if wishbone_in.cyc = '1' then
case state is case state is
when IDLE => when IDLE =>
if wishbone_in.stb = '1' then if wishbone_in.stb = '1' then
-- write -- write
if wishbone_in.we = '1' then if wishbone_in.we = '1' then
assert not(is_x(wishbone_in.dat)) and not(is_x(wishbone_in.adr)) severity failure; assert not(is_x(wishbone_in.dat)) and not(is_x(wishbone_in.adr)) severity failure;
report "RAM writing " & to_hstring(wishbone_in.dat) & " to " & to_hstring(wishbone_in.adr); report "RAM writing " & to_hstring(wishbone_in.dat) & " to " & to_hstring(wishbone_in.adr);
behavioural_write(wishbone_in.dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier); behavioural_write(wishbone_in.dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier);
reload <= reload + 1; reload <= reload + 1;
ret_ack <= '1'; ret_ack <= '1';
state <= ACK; state <= ACK;
else else
behavioural_read(ret_dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier, reload); behavioural_read(ret_dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier, reload);
report "RAM reading from " & to_hstring(wishbone_in.adr) & " returns " & to_hstring(ret_dat); report "RAM reading from " & to_hstring(wishbone_in.adr) & " returns " & to_hstring(ret_dat);
ret_ack <= '1'; ret_ack <= '1';
state <= ACK; state <= ACK;
end if; end if;
end if; end if;
when ACK => when ACK =>
ret_ack <= '0'; ret_ack <= '0';
state <= IDLE; state <= IDLE;
end case; end case;
else else
ret_ack <= '0'; ret_ack <= '0';
state <= IDLE; state <= IDLE;
end if; end if;
end if; end if;
end if; end if;
end process; end process;
end behave; end behave;

36
simple_ram_behavioural_helpers.vhdl
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@ -2,29 +2,29 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;


package simple_ram_behavioural_helpers is package simple_ram_behavioural_helpers is
function behavioural_initialize (filename: String; size: integer) return integer; function behavioural_initialize (filename: String; size: integer) return integer;
attribute foreign of behavioural_initialize : function is "VHPIDIRECT behavioural_initialize"; attribute foreign of behavioural_initialize : function is "VHPIDIRECT behavioural_initialize";


procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer); procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer);
attribute foreign of behavioural_read : procedure is "VHPIDIRECT behavioural_read"; attribute foreign of behavioural_read : procedure is "VHPIDIRECT behavioural_read";


procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer); procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer);
attribute foreign of behavioural_write : procedure is "VHPIDIRECT behavioural_write"; attribute foreign of behavioural_write : procedure is "VHPIDIRECT behavioural_write";
end simple_ram_behavioural_helpers; end simple_ram_behavioural_helpers;


package body simple_ram_behavioural_helpers is package body simple_ram_behavioural_helpers is
function behavioural_initialize (filename: String; size: integer) return integer is function behavioural_initialize (filename: String; size: integer) return integer is
begin begin
assert false report "VHPI" severity failure; assert false report "VHPI" severity failure;
end behavioural_initialize; end behavioural_initialize;


procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer) is procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer; reload: integer) is
begin begin
assert false report "VHPI" severity failure; assert false report "VHPI" severity failure;
end behavioural_read; end behavioural_read;


procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer) is procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer) is
begin begin
assert false report "VHPI" severity failure; assert false report "VHPI" severity failure;
end behavioural_write; end behavioural_write;
end simple_ram_behavioural_helpers; end simple_ram_behavioural_helpers;

444
simple_ram_behavioural_tb.vhdl
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@ -9,225 +9,233 @@ entity simple_ram_behavioural_tb is
end simple_ram_behavioural_tb; end simple_ram_behavioural_tb;


architecture behave of simple_ram_behavioural_tb is architecture behave of simple_ram_behavioural_tb is
signal clk : std_ulogic; signal clk : std_ulogic;
signal rst : std_ulogic := '1'; signal rst : std_ulogic := '1';


constant clk_period : time := 10 ns; constant clk_period : time := 10 ns;


signal w_in : wishbone_slave_out; signal w_in : wishbone_slave_out;
signal w_out : wishbone_master_out; signal w_out : wishbone_master_out;
begin begin
simple_ram_0: entity work.mw_soc_memory simple_ram_0: entity work.mw_soc_memory
generic map ( RAM_INIT_FILE => "simple_ram_behavioural_tb.bin", MEMORY_SIZE => 16 ) generic map (
port map (clk => clk, rst => rst, wishbone_out => w_in, wishbone_in => w_out); RAM_INIT_FILE => "simple_ram_behavioural_tb.bin",

MEMORY_SIZE => 16
clock: process )
begin port map (
clk <= '1'; clk => clk,
wait for clk_period / 2; rst => rst,
clk <= '0'; wishbone_out => w_in,
wait for clk_period / 2; wishbone_in => w_out
end process clock; );


stim: process clock: process
begin begin
w_out.adr <= (others => '0'); clk <= '1';
w_out.dat <= (others => '0'); wait for clk_period / 2;
w_out.cyc <= '0'; clk <= '0';
w_out.stb <= '0'; wait for clk_period / 2;
w_out.sel <= (others => '0'); end process clock;
w_out.we <= '0';

stim: process
wait for clk_period; begin
rst <= '0'; w_out.adr <= (others => '0');

w_out.dat <= (others => '0');
wait for clk_period; w_out.cyc <= '0';

w_out.stb <= '0';
w_out.cyc <= '1'; w_out.sel <= (others => '0');

w_out.we <= '0';
-- test various read lengths and alignments
w_out.stb <= '1'; wait for clk_period;
w_out.sel <= "00000001"; rst <= '0';
w_out.adr <= x"0000000000000000";
assert w_in.ack = '0'; wait for clk_period;
wait for clk_period;
assert w_in.ack = '1'; w_out.cyc <= '1';
assert w_in.dat(7 downto 0) = x"00" report to_hstring(w_in.dat);
w_out.stb <= '0'; -- test various read lengths and alignments
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000001";

w_out.adr <= x"0000000000000000";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00000001"; wait for clk_period;
w_out.adr <= x"0000000000000001"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(7 downto 0) = x"00" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(7 downto 0) = x"01" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000001";

w_out.adr <= x"0000000000000001";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00000001"; wait for clk_period;
w_out.adr <= x"0000000000000007"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(7 downto 0) = x"01" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(7 downto 0) = x"07" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000001";

w_out.adr <= x"0000000000000007";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00000011"; wait for clk_period;
w_out.adr <= x"0000000000000000"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(7 downto 0) = x"07" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(15 downto 0) = x"0100" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000011";

w_out.adr <= x"0000000000000000";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00000011"; wait for clk_period;
w_out.adr <= x"0000000000000001"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(15 downto 0) = x"0100" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(15 downto 0) = x"0201" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000011";

w_out.adr <= x"0000000000000001";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00000011"; wait for clk_period;
w_out.adr <= x"0000000000000007"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(15 downto 0) = x"0201" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(15 downto 0) = x"0807" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00000011";

w_out.adr <= x"0000000000000007";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00001111"; wait for clk_period;
w_out.adr <= x"0000000000000000"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(15 downto 0) = x"0807" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(31 downto 0) = x"03020100" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00001111";

w_out.adr <= x"0000000000000000";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00001111"; wait for clk_period;
w_out.adr <= x"0000000000000001"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(31 downto 0) = x"03020100" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(31 downto 0) = x"04030201" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00001111";

w_out.adr <= x"0000000000000001";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "00001111"; wait for clk_period;
w_out.adr <= x"0000000000000007"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(31 downto 0) = x"04030201" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(31 downto 0) = x"0A090807" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "00001111";

w_out.adr <= x"0000000000000007";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "11111111"; wait for clk_period;
w_out.adr <= x"0000000000000000"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(31 downto 0) = x"0A090807" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "11111111";

w_out.adr <= x"0000000000000000";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "11111111"; wait for clk_period;
w_out.adr <= x"0000000000000001"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(63 downto 0) = x"0807060504030201" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "11111111";

w_out.adr <= x"0000000000000001";
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "11111111"; wait for clk_period;
w_out.adr <= x"0000000000000007"; assert w_in.ack = '1';
assert w_in.ack = '0'; assert w_in.dat(63 downto 0) = x"0807060504030201" report to_hstring(w_in.dat);
wait for clk_period; w_out.stb <= '0';
assert w_in.ack = '1'; wait for clk_period;
assert w_in.dat(63 downto 0) = x"0E0D0C0B0A090807" report to_hstring(w_in.dat); assert w_in.ack = '0';
w_out.stb <= '0';
wait for clk_period; w_out.stb <= '1';
assert w_in.ack = '0'; w_out.sel <= "11111111";

w_out.adr <= x"0000000000000007";
-- test various write lengths and alignments assert w_in.ack = '0';
w_out.stb <= '1'; wait for clk_period;
w_out.sel <= "00000001"; assert w_in.ack = '1';
w_out.adr <= x"0000000000000000"; assert w_in.dat(63 downto 0) = x"0E0D0C0B0A090807" report to_hstring(w_in.dat);
w_out.we <= '1'; w_out.stb <= '0';
w_out.dat(7 downto 0) <= x"0F"; wait for clk_period;
assert w_in.ack = '0'; assert w_in.ack = '0';
wait for clk_period;
assert w_in.ack = '1'; -- test various write lengths and alignments
w_out.stb <= '0'; w_out.stb <= '1';
wait for clk_period; w_out.sel <= "00000001";
assert w_in.ack = '0'; w_out.adr <= x"0000000000000000";

w_out.we <= '1';
w_out.stb <= '1'; w_out.dat(7 downto 0) <= x"0F";
w_out.sel <= "00000001"; assert w_in.ack = '0';
w_out.adr <= x"0000000000000000"; wait for clk_period;
w_out.we <= '0'; assert w_in.ack = '1';
assert w_in.ack = '0'; w_out.stb <= '0';
wait for clk_period; wait for clk_period;
assert w_in.ack = '1'; assert w_in.ack = '0';
assert w_in.dat(7 downto 0) = x"0F" report to_hstring(w_in.dat);
w_out.stb <= '0'; w_out.stb <= '1';
wait for clk_period; w_out.sel <= "00000001";
assert w_in.ack = '0'; w_out.adr <= x"0000000000000000";

w_out.we <= '0';
w_out.stb <= '1'; assert w_in.ack = '0';
w_out.sel <= "11111111"; wait for clk_period;
w_out.adr <= x"0000000000000007"; assert w_in.ack = '1';
w_out.we <= '1'; assert w_in.dat(7 downto 0) = x"0F" report to_hstring(w_in.dat);
w_out.dat <= x"BADC0FFEBADC0FFE"; w_out.stb <= '0';
assert w_in.ack = '0'; wait for clk_period;
wait for clk_period; assert w_in.ack = '0';
assert w_in.ack = '1';
w_out.stb <= '0'; w_out.stb <= '1';
wait for clk_period; w_out.sel <= "11111111";
assert w_in.ack = '0'; w_out.adr <= x"0000000000000007";

w_out.we <= '1';
w_out.stb <= '1'; w_out.dat <= x"BADC0FFEBADC0FFE";
w_out.sel <= "11111111"; assert w_in.ack = '0';
w_out.adr <= x"0000000000000007"; wait for clk_period;
w_out.we <= '0'; assert w_in.ack = '1';
assert w_in.ack = '0'; w_out.stb <= '0';
wait for clk_period; wait for clk_period;
assert w_in.ack = '1'; assert w_in.ack = '0';
assert w_in.dat = x"BADC0FFEBADC0FFE" report to_hstring(w_in.dat);
w_out.stb <= '0'; w_out.stb <= '1';
wait for clk_period; w_out.sel <= "11111111";
assert w_in.ack = '0'; w_out.adr <= x"0000000000000007";

w_out.we <= '0';
assert false report "end of test" severity failure; assert w_in.ack = '0';
wait; wait for clk_period;
end process; assert w_in.ack = '1';
assert w_in.dat = x"BADC0FFEBADC0FFE" report to_hstring(w_in.dat);
w_out.stb <= '0';
wait for clk_period;
assert w_in.ack = '0';

assert false report "end of test" severity failure;
wait;
end process;
end behave; end behave;

84
wishbone_arbiter.vhdl
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@ -5,53 +5,53 @@ library work;
use work.wishbone_types.all; use work.wishbone_types.all;


entity wishbone_arbiter is entity wishbone_arbiter is
port ( port (
clk : in std_ulogic; clk : in std_ulogic;
rst : in std_ulogic; rst : in std_ulogic;


wb1_in : in wishbone_master_out; wb1_in : in wishbone_master_out;
wb1_out : out wishbone_slave_out; wb1_out : out wishbone_slave_out;


wb2_in : in wishbone_master_out; wb2_in : in wishbone_master_out;
wb2_out : out wishbone_slave_out; wb2_out : out wishbone_slave_out;


wb_out : out wishbone_master_out; wb_out : out wishbone_master_out;
wb_in : in wishbone_slave_out wb_in : in wishbone_slave_out
); );
end wishbone_arbiter; end wishbone_arbiter;


architecture behave of wishbone_arbiter is architecture behave of wishbone_arbiter is
type wishbone_arbiter_state_t is (IDLE, WB1_BUSY, WB2_BUSY); type wishbone_arbiter_state_t is (IDLE, WB1_BUSY, WB2_BUSY);
signal state : wishbone_arbiter_state_t := IDLE; signal state : wishbone_arbiter_state_t := IDLE;
begin begin
wb1_out <= wb_in when state = WB1_BUSY else wishbone_slave_out_init; wb1_out <= wb_in when state = WB1_BUSY else wishbone_slave_out_init;
wb2_out <= wb_in when state = WB2_BUSY else wishbone_slave_out_init; wb2_out <= wb_in when state = WB2_BUSY else wishbone_slave_out_init;


wb_out <= wb1_in when state = WB1_BUSY else wb2_in when state = WB2_BUSY else wishbone_master_out_init; wb_out <= wb1_in when state = WB1_BUSY else wb2_in when state = WB2_BUSY else wishbone_master_out_init;


wishbone_arbiter_process: process(clk) wishbone_arbiter_process: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
state <= IDLE; state <= IDLE;
else else
case state is case state is
when IDLE => when IDLE =>
if wb1_in.cyc = '1' then if wb1_in.cyc = '1' then
state <= WB1_BUSY; state <= WB1_BUSY;
elsif wb2_in.cyc = '1' then elsif wb2_in.cyc = '1' then
state <= WB2_BUSY; state <= WB2_BUSY;
end if; end if;
when WB1_BUSY => when WB1_BUSY =>
if wb1_in.cyc = '0' then if wb1_in.cyc = '0' then
state <= IDLE; state <= IDLE;
end if; end if;
when WB2_BUSY => when WB2_BUSY =>
if wb2_in.cyc = '0' then if wb2_in.cyc = '0' then
state <= IDLE; state <= IDLE;
end if; end if;
end case; end case;
end if; end if;
end if; end if;
end process; end process;
end behave; end behave;

36
wishbone_types.vhdl
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@ -2,26 +2,26 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;


package wishbone_types is package wishbone_types is
constant wishbone_addr_bits : integer := 64; constant wishbone_addr_bits : integer := 64;
constant wishbone_data_bits : integer := 64; constant wishbone_data_bits : integer := 64;


subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0); subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0); subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);


type wishbone_master_out is record type wishbone_master_out is record
adr : wishbone_addr_type; adr : wishbone_addr_type;
dat : wishbone_data_type; dat : wishbone_data_type;
cyc : std_ulogic; cyc : std_ulogic;
stb : std_ulogic; stb : std_ulogic;
sel : std_ulogic_vector(7 downto 0); sel : std_ulogic_vector(7 downto 0);
we : std_ulogic; we : std_ulogic;
end record; end record;
constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0')); constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0'));


type wishbone_slave_out is record type wishbone_slave_out is record
dat : wishbone_data_type; dat : wishbone_data_type;
ack : std_ulogic; ack : std_ulogic;
end record; end record;
constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0')); constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0'));


end package wishbone_types; end package wishbone_types;

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