Merge pull request #64 from antonblanchard/reformat-3

Reformat some more files

simple_ram_behavioural_tb.vhdl

@@ -18,8 +18,16 @@ architecture behave of simple_ram_behavioural_tb is
     signal w_out        : wishbone_master_out;
 begin
     simple_ram_0: entity work.mw_soc_memory
-		generic map ( RAM_INIT_FILE => "simple_ram_behavioural_tb.bin", MEMORY_SIZE => 16 )
-		port map (clk => clk, rst => rst, wishbone_out => w_in, wishbone_in => w_out);
+        generic map (
+            RAM_INIT_FILE => "simple_ram_behavioural_tb.bin",
+            MEMORY_SIZE => 16
+            )
+        port map (
+            clk => clk,
+            rst => rst,
+            wishbone_out => w_in,
+            wishbone_in => w_out
+            );
 
     clock: process
     begin