Merge pull request #96 from antonblanchard/clk_gen_bypass-fix

Fix clk_gen_bypass
jtag-port
Anton Blanchard 5 years ago committed by GitHub
commit 56908edea2
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@ -2,6 +2,11 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;


entity clock_generator is entity clock_generator is
generic (
CLK_INPUT_HZ : positive := 50000000;
CLK_OUTPUT_HZ : positive := 50000000
);

port ( port (
ext_clk : in std_logic; ext_clk : in std_logic;
pll_rst_in : in std_logic; pll_rst_in : in std_logic;
@ -13,8 +18,8 @@ end entity clock_generator;
architecture bypass of clock_generator is architecture bypass of clock_generator is


begin begin
assert CLK_INPUT_HZ = CLK_OUTPUT_HZ severity FAILURE;


pll_locked_out <= not pll_rst_in; pll_locked_out <= not pll_rst_in;
pll_clk_out <= ext_clk; pll_clk_out <= ext_clk;

end architecture bypass; end architecture bypass;

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