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@ -0,0 +1,421 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.sim_console.all;
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entity uart_top is
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port(
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wb_clk_i : in std_ulogic;
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wb_rst_i : in std_ulogic;
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wb_adr_i : in std_ulogic_vector(2 downto 0);
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wb_dat_i : in std_ulogic_vector(7 downto 0);
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wb_dat_o : out std_ulogic_vector(7 downto 0);
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wb_we_i : in std_ulogic;
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wb_stb_i : in std_ulogic;
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wb_cyc_i : in std_ulogic;
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wb_ack_o : out std_ulogic;
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int_o : out std_ulogic;
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stx_pad_o : out std_ulogic;
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srx_pad_i : in std_ulogic;
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rts_pad_o : out std_ulogic;
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cts_pad_i : in std_ulogic;
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dtr_pad_o : out std_ulogic;
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dsr_pad_i : in std_ulogic;
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ri_pad_i : in std_ulogic;
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dcd_pad_i : in std_ulogic
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);
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end entity uart_top;
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architecture behaviour of uart_top is
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-- Call POLL every N clocks to generate interrupts
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constant POLL_DELAY : natural := 100;
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-- Register definitions
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subtype reg_adr_t is std_ulogic_vector(2 downto 0);
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constant REG_IDX_RXTX : reg_adr_t := "000";
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constant REG_IDX_IER : reg_adr_t := "001";
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constant REG_IDX_IIR_FCR : reg_adr_t := "010";
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constant REG_IDX_LCR : reg_adr_t := "011";
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constant REG_IDX_MCR : reg_adr_t := "100";
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constant REG_IDX_LSR : reg_adr_t := "101";
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constant REG_IDX_MSR : reg_adr_t := "110";
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constant REG_IDX_SCR : reg_adr_t := "111";
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-- IER bits
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constant REG_IER_RDI_BIT : natural := 0;
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constant REG_IER_THRI_BIT : natural := 1;
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constant REG_IER_RLSI_BIT : natural := 2;
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constant REG_IER_MSI_BIT : natural := 3;
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-- IIR bit
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constant REG_IIR_NO_INT : natural := 0;
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-- IIR values for bit 3 downto 0
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constant REG_IIR_RDI : std_ulogic_vector(3 downto 1) := "010";
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constant REG_IIR_THRI : std_ulogic_vector(3 downto 1) := "001";
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constant REG_IIR_RLSI : std_ulogic_vector(3 downto 1) := "011";
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constant REG_IIR_MSI : std_ulogic_vector(3 downto 1) := "000";
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-- FCR bits
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constant REG_FCR_EN_FIFO_BIT : natural := 0; -- Always 1
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constant REG_FCR_CLR_RCVR_BIT : natural := 1;
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constant REG_FCR_CLR_XMIT_BIT : natural := 2;
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constant REG_FCR_DMA_SEL_BIT : natural := 3; -- Not implemented
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-- FCR values for FIFO threshold in bits 7 downto 6
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constant REG_FCR_FIFO_TRIG1 : std_ulogic_vector(7 downto 6) := "00";
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constant REG_FCR_FIFO_TRIG4 : std_ulogic_vector(7 downto 6) := "01";
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constant REG_FCR_FIFO_TRIG8 : std_ulogic_vector(7 downto 6) := "10";
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constant REG_FCR_FIFO_TRIG14 : std_ulogic_vector(7 downto 6) := "11";
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-- LCR bits
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constant REG_LCR_STOP_BIT : natural := 2;
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constant REG_LCR_PARITY_BIT : natural := 3;
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constant REG_LCR_EPAR_BIT : natural := 4;
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constant REG_LCR_SPAR_BIT : natural := 5;
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constant REG_LCR_SBC_BIT : natural := 6;
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constant REG_LCR_DLAB_BIT : natural := 7;
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-- LCR values for data length (bits 1 downto 0)
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constant REG_LCR_WLEN5 : std_ulogic_vector(1 downto 0) := "00";
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constant REG_LCR_WLEN6 : std_ulogic_vector(1 downto 0) := "01";
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constant REG_LCR_WLEN7 : std_ulogic_vector(1 downto 0) := "10";
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constant REG_LCR_WLEN8 : std_ulogic_vector(1 downto 0) := "11";
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-- MCR bits
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constant REG_MCR_DTR_BIT : natural := 0;
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constant REG_MCR_RTS_BIT : natural := 1;
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constant REG_MCR_OUT1_BIT : natural := 2;
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constant REG_MCR_OUT2_BIT : natural := 3;
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constant REG_MCR_LOOP_BIT : natural := 4;
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-- LSR bits
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constant REG_LSR_DR_BIT : natural := 0;
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constant REG_LSR_OE_BIT : natural := 1;
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constant REG_LSR_PE_BIT : natural := 2;
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constant REG_LSR_FE_BIT : natural := 3;
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constant REG_LSR_BI_BIT : natural := 4;
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constant REG_LSR_THRE_BIT : natural := 5;
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constant REG_LSR_TEMT_BIT : natural := 6;
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constant REG_LSR_FIFOE_BIT : natural := 7;
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-- MSR bits
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constant REG_MSR_DCTS_BIT : natural := 0;
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constant REG_MSR_DDSR_BIT : natural := 1;
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constant REG_MSR_TERI_BIT : natural := 2;
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constant REG_MSR_DDCD_BIT : natural := 3;
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constant REG_MSR_CTS_BIT : natural := 4;
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constant REG_MSR_DSR_BIT : natural := 5;
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constant REG_MSR_RI_BIT : natural := 6;
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constant REG_MSR_DCD_BIT : natural := 7;
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-- Wishbone signals decode:
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signal reg_idx : reg_adr_t;
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signal wb_phase : std_ulogic;
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signal reg_write : std_ulogic;
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signal reg_read : std_ulogic;
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-- Register storage
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signal reg_ier : std_ulogic_vector(3 downto 0);
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signal reg_iir : std_ulogic_vector(3 downto 0);
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signal reg_fcr : std_ulogic_vector(7 downto 6);
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signal reg_lcr : std_ulogic_vector(7 downto 0);
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signal reg_mcr : std_ulogic_vector(4 downto 0);
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signal reg_lsr : std_ulogic_vector(7 downto 0);
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signal reg_msr : std_ulogic_vector(7 downto 0);
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signal reg_scr : std_ulogic_vector(7 downto 0);
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signal reg_div : std_ulogic_vector(15 downto 0);
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-- Control signals
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signal rx_fifo_clr : std_ulogic;
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signal tx_fifo_clr : std_ulogic;
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-- Pending interrupts
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signal int_rdi_pending : std_ulogic;
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signal int_thri_pending : std_ulogic;
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signal int_rlsi_pending : std_ulogic;
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signal int_msi_pending : std_ulogic;
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-- Actual data output
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signal data_out : std_ulogic_vector(7 downto 0) := x"00";
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-- Incoming data pending signal
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signal data_in_pending : std_ulogic := '0';
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-- Useful aliases
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alias dlab : std_ulogic is reg_lcr(REG_LCR_DLAB_BIT);
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alias clk : std_ulogic is wb_clk_i;
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alias rst : std_ulogic is wb_rst_i;
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alias cyc : std_ulogic is wb_cyc_i;
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alias stb : std_ulogic is wb_stb_i;
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alias we : std_ulogic is wb_we_i;
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begin
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-- Register index shortcut
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reg_idx <= wb_adr_i(2 downto 0);
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-- 2 phases WB process.
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--
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-- Among others, this gives us a "free" cycle for the
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-- side effects of some accesses percolate in the form
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-- of status bit changes in other registers.
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wb_cycle: process(clk)
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variable phase : std_ulogic := '0';
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begin
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if rising_edge(clk) then
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if wb_phase = '0' then
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if cyc = '1' and stb = '1' then
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wb_ack_o <= '1';
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wb_phase <= '1';
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end if;
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else
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wb_ack_o <= '0';
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wb_phase <= '0';
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end if;
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end if;
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end process;
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-- Reg read/write signals
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reg_write <= cyc and stb and we and not wb_phase;
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reg_read <= cyc and stb and not we and not wb_phase;
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-- Register read is synchronous to avoid collisions with
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-- read-clear side effects
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do_reg_read: process(clk)
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begin
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if rising_edge(clk) then
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wb_dat_o <= x"00";
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if reg_read = '1' then
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case reg_idx is
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when REG_IDX_RXTX =>
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if dlab = '1' then
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wb_dat_o <= reg_div(7 downto 0);
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else
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wb_dat_o <= data_out;
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end if;
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when REG_IDX_IER =>
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if dlab = '1' then
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wb_dat_o <= reg_div(15 downto 8);
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else
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wb_dat_o <= "0000" & reg_ier;
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end if;
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when REG_IDX_IIR_FCR =>
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-- Top bits always set as FIFO is always enabled
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wb_dat_o <= "1100" & reg_iir;
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when REG_IDX_LCR =>
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wb_dat_o <= reg_lcr;
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when REG_IDX_LSR =>
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wb_dat_o <= reg_lsr;
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when REG_IDX_MSR =>
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wb_dat_o <= reg_msr;
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when REG_IDX_SCR =>
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wb_dat_o <= reg_scr;
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when others =>
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end case;
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end if;
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end if;
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end process;
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-- Receive/send synchronous process
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rxtx: process(clk)
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variable dp : std_ulogic;
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variable poll_cnt : natural;
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variable sim_tmp : std_ulogic_vector(63 downto 0);
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begin
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if rising_edge(clk) then
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if rst = '0' then
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dp := data_in_pending;
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if dlab = '0' and reg_idx = REG_IDX_RXTX then
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if reg_write = '1' then
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-- FIFO write
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-- XXX Simulate the FIFO and delays for more
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-- accurate behaviour & interrupts
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sim_console_write(x"00000000000000" & wb_dat_i);
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end if;
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if reg_read = '1' then
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dp := '0';
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data_out <= x"00";
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end if;
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end if;
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-- Poll for incoming data
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if poll_cnt = 0 or (reg_read = '1' and reg_idx = REG_IDX_LSR) then
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sim_console_poll(sim_tmp);
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poll_cnt := POLL_DELAY;
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if dp = '0' and sim_tmp(0) = '1' then
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dp := '1';
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sim_console_read(sim_tmp);
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data_out <= sim_tmp(7 downto 0);
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end if;
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poll_cnt := poll_cnt - 1;
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end if;
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data_in_pending <= dp;
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end if;
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end if;
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end process;
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-- Interrupt pending bits
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int_rdi_pending <= data_in_pending;
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int_thri_pending <= '1';
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int_rlsi_pending <= reg_lsr(REG_LSR_OE_BIT) or
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reg_lsr(REG_LSR_PE_BIT) or
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reg_lsr(REG_LSR_FE_BIT) or
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reg_lsr(REG_LSR_BI_BIT);
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int_msi_pending <= reg_msr(REG_MSR_DCTS_BIT) or
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reg_msr(REG_MSR_DDSR_BIT) or
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reg_msr(REG_MSR_TERI_BIT) or
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reg_msr(REG_MSR_DDCD_BIT);
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-- Derive interrupt output from IIR
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int_o <= not reg_iir(REG_IIR_NO_INT);
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-- Divisor register
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div_reg_w: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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reg_div <= (others => '0');
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elsif reg_write = '1' and dlab = '1' then
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if reg_idx = REG_IDX_RXTX then
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reg_div(7 downto 0) <= wb_dat_i;
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elsif reg_idx = REG_IDX_IER then
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reg_div(15 downto 8) <= wb_dat_i;
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end if;
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end if;
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end if;
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end process;
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-- IER register
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ier_reg_w: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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reg_ier <= "0000";
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else
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if reg_write = '1' and dlab = '0' and reg_idx = REG_IDX_IER then
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reg_ier <= wb_dat_i(3 downto 0);
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end if;
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end if;
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end if;
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end process;
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-- IIR (read only) generation
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iir_reg_w: process(clk)
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begin
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if rising_edge(clk) then
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reg_iir <= "0001";
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if int_rlsi_pending = '1' and reg_ier(REG_IER_RLSI_BIT) = '1' then
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reg_iir <= REG_IIR_RLSI & "0";
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elsif int_rdi_pending = '1' and reg_ier(REG_IER_RDI_BIT) = '1' then
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reg_iir <= REG_IIR_RDI & "0";
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elsif int_thri_pending = '1' and reg_ier(REG_IER_THRI_BIT) = '1' then
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reg_iir <= REG_IIR_THRI & "0";
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elsif int_msi_pending = '1' and reg_ier(REG_IER_MSI_BIT) = '1' then
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reg_iir <= REG_IIR_MSI & "0";
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end if;
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-- It *seems* like reading IIR should clear THRI for
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-- some amount of time until it gets set again a few
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-- clocks later if the transmitter is still empty. We
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-- don't do that at this point.
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end if;
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end process;
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-- FCR (write only) register
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fcr_reg_w: process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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reg_fcr <= "11";
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rx_fifo_clr <= '1';
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tx_fifo_clr <= '1';
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elsif reg_write = '1' and reg_idx = REG_IDX_IIR_FCR then
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reg_fcr <= wb_dat_i(7 downto 6);
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rx_fifo_clr <= wb_dat_i(REG_FCR_CLR_RCVR_BIT);
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tx_fifo_clr <= wb_dat_i(REG_FCR_CLR_XMIT_BIT);
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else
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rx_fifo_clr <= '0';
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tx_fifo_clr <= '0';
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end if;
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end if;
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end process;
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-- LCR register
|
||||||
|
lcr_reg_w: process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if rst = '1' then
|
||||||
|
reg_lcr <= "00000011";
|
||||||
|
elsif reg_write = '1' and reg_idx = REG_IDX_LCR then
|
||||||
|
reg_lcr <= wb_dat_i;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- MCR register
|
||||||
|
mcr_reg_w: process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if rst = '1' then
|
||||||
|
reg_mcr <= "00000";
|
||||||
|
elsif reg_write = '1' and reg_idx = REG_IDX_MCR then
|
||||||
|
reg_mcr <= wb_dat_i(4 downto 0);
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- LSR register
|
||||||
|
lsr_reg_w: process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if rst = '1' then
|
||||||
|
reg_lsr <= "00000000";
|
||||||
|
else
|
||||||
|
reg_lsr(REG_LSR_DR_BIT) <= data_in_pending;
|
||||||
|
|
||||||
|
-- Clear error bits on read. Those bits are
|
||||||
|
-- always 0 in sim for now.
|
||||||
|
-- if reg_read = '1' and reg_idx = REG_IDX_LSR then
|
||||||
|
-- reg_lsr(REG_LSR_OE_BIT) <= '0';
|
||||||
|
-- reg_lsr(REG_LSR_PE_BIT) <= '0';
|
||||||
|
-- reg_lsr(REG_LSR_FE_BIT) <= '0';
|
||||||
|
-- reg_lsr(REG_LSR_BI_BIT) <= '0';
|
||||||
|
-- reg_lsr(REG_LSR_FIFOE_BIT) <= '0';
|
||||||
|
-- end if;
|
||||||
|
|
||||||
|
-- Tx FIFO empty indicators. Always empty in sim
|
||||||
|
reg_lsr(REG_LSR_THRE_BIT) <= '1';
|
||||||
|
reg_lsr(REG_LSR_TEMT_BIT) <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- MSR register
|
||||||
|
msr_reg_w: process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if rst = '1' then
|
||||||
|
reg_msr <= "00000000";
|
||||||
|
elsif reg_read = '1' and reg_idx = REG_IDX_MSR then
|
||||||
|
reg_msr <= "00000000";
|
||||||
|
-- XXX TODO bit setting machine...
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- SCR register
|
||||||
|
scr_reg_w: process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if rst = '1' then
|
||||||
|
reg_scr <= "00000000";
|
||||||
|
elsif reg_write = '1' and reg_idx = REG_IDX_SCR then
|
||||||
|
reg_scr <= wb_dat_i;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end architecture behaviour;
|
||||||
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Reference in New Issue