@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:39
// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:54
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
module litedram_core(
module litedram_core(
input wire clk,
input wire clk,
@ -33,8 +33,8 @@ module litedram_core(
reg [13:0] litedramcore_adr = 14'd0;
reg [13:0] litedramcore_adr = 14'd0;
reg litedramcore_we = 1'd0;
reg litedramcore_we = 1'd0;
wire [7:0] litedramcore_dat_w;
wire [31:0] litedramcore_dat_w;
wire [7:0] litedramcore_dat_r;
wire [31:0] litedramcore_dat_r;
wire [29:0] litedramcore_wishbone_adr;
wire [29:0] litedramcore_wishbone_adr;
wire [31:0] litedramcore_wishbone_dat_w;
wire [31:0] litedramcore_wishbone_dat_w;
wire [31:0] litedramcore_wishbone_dat_r;
wire [31:0] litedramcore_wishbone_dat_r;
@ -1638,8 +1638,8 @@ reg new_master_rdata_valid8 = 1'd0;
reg new_master_rdata_valid9 = 1'd0;
reg new_master_rdata_valid9 = 1'd0;
wire [13:0] interface0_bank_bus_adr;
wire [13:0] interface0_bank_bus_adr;
wire interface0_bank_bus_we;
wire interface0_bank_bus_we;
wire [7:0] interface0_bank_bus_dat_w;
wire [31:0] interface0_bank_bus_dat_w;
reg [7:0] interface0_bank_bus_dat_r = 8'd0;
reg [31:0] interface0_bank_bus_dat_r = 32'd0;
wire csrbank0_init_done0_re;
wire csrbank0_init_done0_re;
wire csrbank0_init_done0_r;
wire csrbank0_init_done0_r;
wire csrbank0_init_done0_we;
wire csrbank0_init_done0_we;
@ -1651,8 +1651,8 @@ wire csrbank0_init_error0_w;
wire csrbank0_sel;
wire csrbank0_sel;
wire [13:0] interface1_bank_bus_adr;
wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we;
wire interface1_bank_bus_we;
wire [7:0] interface1_bank_bus_dat_w;
wire [31:0] interface1_bank_bus_dat_w;
reg [7:0] interface1_bank_bus_dat_r = 8'd0;
reg [31:0] interface1_bank_bus_dat_r = 32'd0;
wire csrbank1_dfii_control0_re;
wire csrbank1_dfii_control0_re;
wire [3:0] csrbank1_dfii_control0_r;
wire [3:0] csrbank1_dfii_control0_r;
wire csrbank1_dfii_control0_we;
wire csrbank1_dfii_control0_we;
@ -1661,199 +1661,87 @@ wire csrbank1_dfii_pi0_command0_re;
wire [5:0] csrbank1_dfii_pi0_command0_r;
wire [5:0] csrbank1_dfii_pi0_command0_r;
wire csrbank1_dfii_pi0_command0_we;
wire csrbank1_dfii_pi0_command0_we;
wire [5:0] csrbank1_dfii_pi0_command0_w;
wire [5:0] csrbank1_dfii_pi0_command0_w;
wire csrbank1_dfii_pi0_address1_re;
wire [5:0] csrbank1_dfii_pi0_address1_r;
wire csrbank1_dfii_pi0_address1_we;
wire [5:0] csrbank1_dfii_pi0_address1_w;
wire csrbank1_dfii_pi0_address0_re;
wire csrbank1_dfii_pi0_address0_re;
wire [7:0] csrbank1_dfii_pi0_address0_r;
wire [13:0] csrbank1_dfii_pi0_address0_r;
wire csrbank1_dfii_pi0_address0_we;
wire csrbank1_dfii_pi0_address0_we;
wire [7:0] csrbank1_dfii_pi0_address0_w;
wire [13:0] csrbank1_dfii_pi0_address0_w;
wire csrbank1_dfii_pi0_baddress0_re;
wire csrbank1_dfii_pi0_baddress0_re;
wire [2:0] csrbank1_dfii_pi0_baddress0_r;
wire [2:0] csrbank1_dfii_pi0_baddress0_r;
wire csrbank1_dfii_pi0_baddress0_we;
wire csrbank1_dfii_pi0_baddress0_we;
wire [2:0] csrbank1_dfii_pi0_baddress0_w;
wire [2:0] csrbank1_dfii_pi0_baddress0_w;
wire csrbank1_dfii_pi0_wrdata3_re;
wire [7:0] csrbank1_dfii_pi0_wrdata3_r;
wire csrbank1_dfii_pi0_wrdata3_we;
wire [7:0] csrbank1_dfii_pi0_wrdata3_w;
wire csrbank1_dfii_pi0_wrdata2_re;
wire [7:0] csrbank1_dfii_pi0_wrdata2_r;
wire csrbank1_dfii_pi0_wrdata2_we;
wire [7:0] csrbank1_dfii_pi0_wrdata2_w;
wire csrbank1_dfii_pi0_wrdata1_re;
wire [7:0] csrbank1_dfii_pi0_wrdata1_r;
wire csrbank1_dfii_pi0_wrdata1_we;
wire [7:0] csrbank1_dfii_pi0_wrdata1_w;
wire csrbank1_dfii_pi0_wrdata0_re;
wire csrbank1_dfii_pi0_wrdata0_re;
wire [7:0] csrbank1_dfii_pi0_wrdata0_r;
wire [31:0] csrbank1_dfii_pi0_wrdata0_r;
wire csrbank1_dfii_pi0_wrdata0_we;
wire csrbank1_dfii_pi0_wrdata0_we;
wire [7:0] csrbank1_dfii_pi0_wrdata0_w;
wire [31:0] csrbank1_dfii_pi0_wrdata0_w;
wire csrbank1_dfii_pi0_rddata3_re;
wire csrbank1_dfii_pi0_rddata_re;
wire [7:0] csrbank1_dfii_pi0_rddata3_r;
wire [31:0] csrbank1_dfii_pi0_rddata_r;
wire csrbank1_dfii_pi0_rddata3_we;
wire csrbank1_dfii_pi0_rddata_we;
wire [7:0] csrbank1_dfii_pi0_rddata3_w;
wire [31:0] csrbank1_dfii_pi0_rddata_w;
wire csrbank1_dfii_pi0_rddata2_re;
wire [7:0] csrbank1_dfii_pi0_rddata2_r;
wire csrbank1_dfii_pi0_rddata2_we;
wire [7:0] csrbank1_dfii_pi0_rddata2_w;
wire csrbank1_dfii_pi0_rddata1_re;
wire [7:0] csrbank1_dfii_pi0_rddata1_r;
wire csrbank1_dfii_pi0_rddata1_we;
wire [7:0] csrbank1_dfii_pi0_rddata1_w;
wire csrbank1_dfii_pi0_rddata0_re;
wire [7:0] csrbank1_dfii_pi0_rddata0_r;
wire csrbank1_dfii_pi0_rddata0_we;
wire [7:0] csrbank1_dfii_pi0_rddata0_w;
wire csrbank1_dfii_pi1_command0_re;
wire csrbank1_dfii_pi1_command0_re;
wire [5:0] csrbank1_dfii_pi1_command0_r;
wire [5:0] csrbank1_dfii_pi1_command0_r;
wire csrbank1_dfii_pi1_command0_we;
wire csrbank1_dfii_pi1_command0_we;
wire [5:0] csrbank1_dfii_pi1_command0_w;
wire [5:0] csrbank1_dfii_pi1_command0_w;
wire csrbank1_dfii_pi1_address1_re;
wire [5:0] csrbank1_dfii_pi1_address1_r;
wire csrbank1_dfii_pi1_address1_we;
wire [5:0] csrbank1_dfii_pi1_address1_w;
wire csrbank1_dfii_pi1_address0_re;
wire csrbank1_dfii_pi1_address0_re;
wire [7:0] csrbank1_dfii_pi1_address0_r;
wire [13:0] csrbank1_dfii_pi1_address0_r;
wire csrbank1_dfii_pi1_address0_we;
wire csrbank1_dfii_pi1_address0_we;
wire [7:0] csrbank1_dfii_pi1_address0_w;
wire [13:0] csrbank1_dfii_pi1_address0_w;
wire csrbank1_dfii_pi1_baddress0_re;
wire csrbank1_dfii_pi1_baddress0_re;
wire [2:0] csrbank1_dfii_pi1_baddress0_r;
wire [2:0] csrbank1_dfii_pi1_baddress0_r;
wire csrbank1_dfii_pi1_baddress0_we;
wire csrbank1_dfii_pi1_baddress0_we;
wire [2:0] csrbank1_dfii_pi1_baddress0_w;
wire [2:0] csrbank1_dfii_pi1_baddress0_w;
wire csrbank1_dfii_pi1_wrdata3_re;
wire [7:0] csrbank1_dfii_pi1_wrdata3_r;
wire csrbank1_dfii_pi1_wrdata3_we;
wire [7:0] csrbank1_dfii_pi1_wrdata3_w;
wire csrbank1_dfii_pi1_wrdata2_re;
wire [7:0] csrbank1_dfii_pi1_wrdata2_r;
wire csrbank1_dfii_pi1_wrdata2_we;
wire [7:0] csrbank1_dfii_pi1_wrdata2_w;
wire csrbank1_dfii_pi1_wrdata1_re;
wire [7:0] csrbank1_dfii_pi1_wrdata1_r;
wire csrbank1_dfii_pi1_wrdata1_we;
wire [7:0] csrbank1_dfii_pi1_wrdata1_w;
wire csrbank1_dfii_pi1_wrdata0_re;
wire csrbank1_dfii_pi1_wrdata0_re;
wire [7:0] csrbank1_dfii_pi1_wrdata0_r;
wire [31:0] csrbank1_dfii_pi1_wrdata0_r;
wire csrbank1_dfii_pi1_wrdata0_we;
wire csrbank1_dfii_pi1_wrdata0_we;
wire [7:0] csrbank1_dfii_pi1_wrdata0_w;
wire [31:0] csrbank1_dfii_pi1_wrdata0_w;
wire csrbank1_dfii_pi1_rddata3_re;
wire csrbank1_dfii_pi1_rddata_re;
wire [7:0] csrbank1_dfii_pi1_rddata3_r;
wire [31:0] csrbank1_dfii_pi1_rddata_r;
wire csrbank1_dfii_pi1_rddata3_we;
wire csrbank1_dfii_pi1_rddata_we;
wire [7:0] csrbank1_dfii_pi1_rddata3_w;
wire [31:0] csrbank1_dfii_pi1_rddata_w;
wire csrbank1_dfii_pi1_rddata2_re;
wire [7:0] csrbank1_dfii_pi1_rddata2_r;
wire csrbank1_dfii_pi1_rddata2_we;
wire [7:0] csrbank1_dfii_pi1_rddata2_w;
wire csrbank1_dfii_pi1_rddata1_re;
wire [7:0] csrbank1_dfii_pi1_rddata1_r;
wire csrbank1_dfii_pi1_rddata1_we;
wire [7:0] csrbank1_dfii_pi1_rddata1_w;
wire csrbank1_dfii_pi1_rddata0_re;
wire [7:0] csrbank1_dfii_pi1_rddata0_r;
wire csrbank1_dfii_pi1_rddata0_we;
wire [7:0] csrbank1_dfii_pi1_rddata0_w;
wire csrbank1_dfii_pi2_command0_re;
wire csrbank1_dfii_pi2_command0_re;
wire [5:0] csrbank1_dfii_pi2_command0_r;
wire [5:0] csrbank1_dfii_pi2_command0_r;
wire csrbank1_dfii_pi2_command0_we;
wire csrbank1_dfii_pi2_command0_we;
wire [5:0] csrbank1_dfii_pi2_command0_w;
wire [5:0] csrbank1_dfii_pi2_command0_w;
wire csrbank1_dfii_pi2_address1_re;
wire [5:0] csrbank1_dfii_pi2_address1_r;
wire csrbank1_dfii_pi2_address1_we;
wire [5:0] csrbank1_dfii_pi2_address1_w;
wire csrbank1_dfii_pi2_address0_re;
wire csrbank1_dfii_pi2_address0_re;
wire [7:0] csrbank1_dfii_pi2_address0_r;
wire [13:0] csrbank1_dfii_pi2_address0_r;
wire csrbank1_dfii_pi2_address0_we;
wire csrbank1_dfii_pi2_address0_we;
wire [7:0] csrbank1_dfii_pi2_address0_w;
wire [13:0] csrbank1_dfii_pi2_address0_w;
wire csrbank1_dfii_pi2_baddress0_re;
wire csrbank1_dfii_pi2_baddress0_re;
wire [2:0] csrbank1_dfii_pi2_baddress0_r;
wire [2:0] csrbank1_dfii_pi2_baddress0_r;
wire csrbank1_dfii_pi2_baddress0_we;
wire csrbank1_dfii_pi2_baddress0_we;
wire [2:0] csrbank1_dfii_pi2_baddress0_w;
wire [2:0] csrbank1_dfii_pi2_baddress0_w;
wire csrbank1_dfii_pi2_wrdata3_re;
wire [7:0] csrbank1_dfii_pi2_wrdata3_r;
wire csrbank1_dfii_pi2_wrdata3_we;
wire [7:0] csrbank1_dfii_pi2_wrdata3_w;
wire csrbank1_dfii_pi2_wrdata2_re;
wire [7:0] csrbank1_dfii_pi2_wrdata2_r;
wire csrbank1_dfii_pi2_wrdata2_we;
wire [7:0] csrbank1_dfii_pi2_wrdata2_w;
wire csrbank1_dfii_pi2_wrdata1_re;
wire [7:0] csrbank1_dfii_pi2_wrdata1_r;
wire csrbank1_dfii_pi2_wrdata1_we;
wire [7:0] csrbank1_dfii_pi2_wrdata1_w;
wire csrbank1_dfii_pi2_wrdata0_re;
wire csrbank1_dfii_pi2_wrdata0_re;
wire [7:0] csrbank1_dfii_pi2_wrdata0_r;
wire [31:0] csrbank1_dfii_pi2_wrdata0_r;
wire csrbank1_dfii_pi2_wrdata0_we;
wire csrbank1_dfii_pi2_wrdata0_we;
wire [7:0] csrbank1_dfii_pi2_wrdata0_w;
wire [31:0] csrbank1_dfii_pi2_wrdata0_w;
wire csrbank1_dfii_pi2_rddata3_re;
wire csrbank1_dfii_pi2_rddata_re;
wire [7:0] csrbank1_dfii_pi2_rddata3_r;
wire [31:0] csrbank1_dfii_pi2_rddata_r;
wire csrbank1_dfii_pi2_rddata3_we;
wire csrbank1_dfii_pi2_rddata_we;
wire [7:0] csrbank1_dfii_pi2_rddata3_w;
wire [31:0] csrbank1_dfii_pi2_rddata_w;
wire csrbank1_dfii_pi2_rddata2_re;
wire [7:0] csrbank1_dfii_pi2_rddata2_r;
wire csrbank1_dfii_pi2_rddata2_we;
wire [7:0] csrbank1_dfii_pi2_rddata2_w;
wire csrbank1_dfii_pi2_rddata1_re;
wire [7:0] csrbank1_dfii_pi2_rddata1_r;
wire csrbank1_dfii_pi2_rddata1_we;
wire [7:0] csrbank1_dfii_pi2_rddata1_w;
wire csrbank1_dfii_pi2_rddata0_re;
wire [7:0] csrbank1_dfii_pi2_rddata0_r;
wire csrbank1_dfii_pi2_rddata0_we;
wire [7:0] csrbank1_dfii_pi2_rddata0_w;
wire csrbank1_dfii_pi3_command0_re;
wire csrbank1_dfii_pi3_command0_re;
wire [5:0] csrbank1_dfii_pi3_command0_r;
wire [5:0] csrbank1_dfii_pi3_command0_r;
wire csrbank1_dfii_pi3_command0_we;
wire csrbank1_dfii_pi3_command0_we;
wire [5:0] csrbank1_dfii_pi3_command0_w;
wire [5:0] csrbank1_dfii_pi3_command0_w;
wire csrbank1_dfii_pi3_address1_re;
wire [5:0] csrbank1_dfii_pi3_address1_r;
wire csrbank1_dfii_pi3_address1_we;
wire [5:0] csrbank1_dfii_pi3_address1_w;
wire csrbank1_dfii_pi3_address0_re;
wire csrbank1_dfii_pi3_address0_re;
wire [7:0] csrbank1_dfii_pi3_address0_r;
wire [13:0] csrbank1_dfii_pi3_address0_r;
wire csrbank1_dfii_pi3_address0_we;
wire csrbank1_dfii_pi3_address0_we;
wire [7:0] csrbank1_dfii_pi3_address0_w;
wire [13:0] csrbank1_dfii_pi3_address0_w;
wire csrbank1_dfii_pi3_baddress0_re;
wire csrbank1_dfii_pi3_baddress0_re;
wire [2:0] csrbank1_dfii_pi3_baddress0_r;
wire [2:0] csrbank1_dfii_pi3_baddress0_r;
wire csrbank1_dfii_pi3_baddress0_we;
wire csrbank1_dfii_pi3_baddress0_we;
wire [2:0] csrbank1_dfii_pi3_baddress0_w;
wire [2:0] csrbank1_dfii_pi3_baddress0_w;
wire csrbank1_dfii_pi3_wrdata3_re;
wire [7:0] csrbank1_dfii_pi3_wrdata3_r;
wire csrbank1_dfii_pi3_wrdata3_we;
wire [7:0] csrbank1_dfii_pi3_wrdata3_w;
wire csrbank1_dfii_pi3_wrdata2_re;
wire [7:0] csrbank1_dfii_pi3_wrdata2_r;
wire csrbank1_dfii_pi3_wrdata2_we;
wire [7:0] csrbank1_dfii_pi3_wrdata2_w;
wire csrbank1_dfii_pi3_wrdata1_re;
wire [7:0] csrbank1_dfii_pi3_wrdata1_r;
wire csrbank1_dfii_pi3_wrdata1_we;
wire [7:0] csrbank1_dfii_pi3_wrdata1_w;
wire csrbank1_dfii_pi3_wrdata0_re;
wire csrbank1_dfii_pi3_wrdata0_re;
wire [7:0] csrbank1_dfii_pi3_wrdata0_r;
wire [31:0] csrbank1_dfii_pi3_wrdata0_r;
wire csrbank1_dfii_pi3_wrdata0_we;
wire csrbank1_dfii_pi3_wrdata0_we;
wire [7:0] csrbank1_dfii_pi3_wrdata0_w;
wire [31:0] csrbank1_dfii_pi3_wrdata0_w;
wire csrbank1_dfii_pi3_rddata3_re;
wire csrbank1_dfii_pi3_rddata_re;
wire [7:0] csrbank1_dfii_pi3_rddata3_r;
wire [31:0] csrbank1_dfii_pi3_rddata_r;
wire csrbank1_dfii_pi3_rddata3_we;
wire csrbank1_dfii_pi3_rddata_we;
wire [7:0] csrbank1_dfii_pi3_rddata3_w;
wire [31:0] csrbank1_dfii_pi3_rddata_w;
wire csrbank1_dfii_pi3_rddata2_re;
wire [7:0] csrbank1_dfii_pi3_rddata2_r;
wire csrbank1_dfii_pi3_rddata2_we;
wire [7:0] csrbank1_dfii_pi3_rddata2_w;
wire csrbank1_dfii_pi3_rddata1_re;
wire [7:0] csrbank1_dfii_pi3_rddata1_r;
wire csrbank1_dfii_pi3_rddata1_we;
wire [7:0] csrbank1_dfii_pi3_rddata1_w;
wire csrbank1_dfii_pi3_rddata0_re;
wire [7:0] csrbank1_dfii_pi3_rddata0_r;
wire csrbank1_dfii_pi3_rddata0_we;
wire [7:0] csrbank1_dfii_pi3_rddata0_w;
wire csrbank1_sel;
wire csrbank1_sel;
wire [13:0] adr;
wire [13:0] adr;
wire we;
wire we;
wire [7:0] dat_w;
wire [31:0] dat_w;
wire [7:0] dat_r;
wire [31:0] dat_r;
wire [24:0] slice_proxy0;
wire [24:0] slice_proxy0;
wire [24:0] slice_proxy1;
wire [24:0] slice_proxy1;
wire [24:0] slice_proxy2;
wire [24:0] slice_proxy2;
@ -9892,217 +9780,105 @@ assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
assign csrbank0_init_error0_w = init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd0));
assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd0));
assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd1));
assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd1));
assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd1));
assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd1));
assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd2));
assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd2));
assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd2));
assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd2));
assign csrbank1_dfii_pi0_address1_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi0_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd3));
assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbank1_dfii_pi0_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd3));
assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd4));
assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd4));
assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd5));
assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd5));
assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi0_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd6));
assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbank1_dfii_pi0_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd6));
assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi0_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd7));
assign csrbank1_dfii_pi0_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbank1_dfii_pi0_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd7));
assign csrbank1_dfii_pi0_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbank1_dfii_pi0_wrdata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd8));
assign csrbank1_dfii_pi0_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd8));
assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd9));
assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd9));
assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd10));
assign csrbank1_dfii_pi0_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd10));
assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd11));
assign csrbank1_dfii_pi0_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd11));
assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd12));
assign csrbank1_dfii_pi0_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd12));
assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi0_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd13));
assign csrbank1_dfii_pi0_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd13));
assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd14));
assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd7));
assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd14));
assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd7));
assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd15));
assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd8));
assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd15));
assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd8));
assign csrbank1_dfii_pi1_address1_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi1_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd16));
assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbank1_dfii_pi1_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd16));
assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd17));
assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd17));
assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd18));
assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd18));
assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi1_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd19));
assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbank1_dfii_pi1_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd19));
assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi1_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd20));
assign csrbank1_dfii_pi1_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbank1_dfii_pi1_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd20));
assign csrbank1_dfii_pi1_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbank1_dfii_pi1_wrdata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd21));
assign csrbank1_dfii_pi1_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd21));
assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd22));
assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd22));
assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd23));
assign csrbank1_dfii_pi1_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd23));
assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd24));
assign csrbank1_dfii_pi1_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd24));
assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd25));
assign csrbank1_dfii_pi1_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd25));
assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi1_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd26));
assign csrbank1_dfii_pi1_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd26));
assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd27));
assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd13));
assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd27));
assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd13));
assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd28));
assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd14));
assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd28));
assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd14));
assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi2_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd29));
assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd15));
assign csrbank1_dfii_pi2_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd29));
assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd15));
assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd30));
assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd30));
assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd31));
assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd31));
assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi2_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd32));
assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd17));
assign csrbank1_dfii_pi2_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd32));
assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd17));
assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi2_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd33));
assign csrbank1_dfii_pi2_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd18));
assign csrbank1_dfii_pi2_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd33));
assign csrbank1_dfii_pi2_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd18));
assign csrbank1_dfii_pi2_wrdata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd34));
assign csrbank1_dfii_pi2_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd34));
assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd35));
assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd35));
assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd36));
assign csrbank1_dfii_pi2_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd36));
assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd37));
assign csrbank1_dfii_pi2_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd37));
assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd38));
assign csrbank1_dfii_pi2_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd38));
assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi2_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd39));
assign csrbank1_dfii_pi2_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd39));
assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd40));
assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd19));
assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd40));
assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd19));
assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd41));
assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd20));
assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd41));
assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd20));
assign csrbank1_dfii_pi3_address1_r = interface1_bank_bus_dat_w[5:0];
assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
assign csrbank1_dfii_pi3_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd42));
assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd21));
assign csrbank1_dfii_pi3_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd42));
assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd21));
assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd43));
assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd43));
assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd44));
assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd22));
assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd44));
assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd22));
assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi3_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd45));
assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd23));
assign csrbank1_dfii_pi3_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd45));
assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd23));
assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
assign csrbank1_dfii_pi3_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd46));
assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd24));
assign csrbank1_dfii_pi3_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd46));
assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd24));
assign csrbank1_dfii_pi3_wrdata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd47));
assign csrbank1_dfii_pi3_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd47));
assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd48));
assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd48));
assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd49));
assign csrbank1_dfii_pi3_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd49));
assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd50));
assign csrbank1_dfii_pi3_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd50));
assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd51));
assign csrbank1_dfii_pi3_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd51));
assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_dfii_pi3_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd52));
assign csrbank1_dfii_pi3_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd52));
assign csrbank1_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank1_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
assign csrbank1_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8];
assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0];
assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
assign csrbank1_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24];
assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
assign csrbank1_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16];
assign csrbank1_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
assign csrbank1_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8];
assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata_we;
assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0];
assign csrbank1_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24];
assign csrbank1_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16];
assign csrbank1_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8];
assign csrbank1_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0];
assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata0_we;
assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
assign csrbank1_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8];
assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0];
assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
assign csrbank1_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24];
assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
assign csrbank1_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16];
assign csrbank1_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
assign csrbank1_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8];
assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata_we;
assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0];
assign csrbank1_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24];
assign csrbank1_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16];
assign csrbank1_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8];
assign csrbank1_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0];
assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata0_we;
assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
assign csrbank1_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8];
assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0];
assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
assign csrbank1_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24];
assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
assign csrbank1_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16];
assign csrbank1_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
assign csrbank1_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8];
assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata_we;
assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0];
assign csrbank1_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24];
assign csrbank1_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16];
assign csrbank1_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8];
assign csrbank1_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0];
assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata0_we;
assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
assign csrbank1_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8];
assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0];
assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
assign csrbank1_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24];
assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
assign csrbank1_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16];
assign csrbank1_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
assign csrbank1_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8];
assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata_we;
assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0];
assign csrbank1_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24];
assign csrbank1_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16];
assign csrbank1_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8];
assign csrbank1_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0];
assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata0_we;
assign adr = litedramcore_adr;
assign adr = litedramcore_adr;
assign we = litedramcore_we;
assign we = litedramcore_we;
assign dat_w = litedramcore_dat_w;
assign dat_w = litedramcore_dat_w;
@ -12768,7 +12544,7 @@ always @(posedge sys_clk) begin
init_error_re <= csrbank0_init_error0_re;
init_error_re <= csrbank0_init_error0_re;
interface1_bank_bus_dat_r <= 1'd0;
interface1_bank_bus_dat_r <= 1'd0;
if (csrbank1_sel) begin
if (csrbank1_sel) begin
case (interface1_bank_bus_adr[5:0])
case (interface1_bank_bus_adr[4:0])
1'd0: begin
1'd0: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
end
end
@ -12779,154 +12555,70 @@ always @(posedge sys_clk) begin
interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
end
end
2'd3: begin
2'd3: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address1_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
end
end
3'd4: begin
3'd4: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
end
end
3'd5: begin
3'd5: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
end
end
3'd6: begin
3'd6: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata3_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
end
end
3'd7: begin
3'd7: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata2_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
end
end
4'd8: begin
4'd8: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata1_w;
interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
end
end
4'd9: begin
4'd9: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
end
end
4'd10: begin
4'd10: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata3_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
end
end
4'd11: begin
4'd11: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata2_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
end
end
4'd12: begin
4'd12: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata1_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
end
end
4'd13: begin
4'd13: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
end
end
4'd14: begin
4'd14: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
end
end
4'd15: begin
4'd15: begin
interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
end
end
5'd16: begin
5'd16: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address1_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
end
end
5'd17: begin
5'd17: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
end
end
5'd18: begin
5'd18: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
end
end
5'd19: begin
5'd19: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata3_w;
end
5'd20: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata2_w;
end
5'd21: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata1_w;
end
5'd22: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
end
5'd23: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata3_w;
end
5'd24: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata2_w;
end
5'd25: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata1_w;
end
5'd26: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata0_w;
end
5'd27: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
end
5'd28: begin
interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
end
5'd29: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address1_w;
end
5'd30: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
end
5'd31: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
end
6'd32: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata3_w;
end
6'd33: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata2_w;
end
6'd34: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata1_w;
end
6'd35: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
end
6'd36: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata3_w;
end
6'd37: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata2_w;
end
6'd38: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata1_w;
end
6'd39: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata0_w;
end
6'd40: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
end
end
6'd41: begin
5'd20: begin
interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
end
end
6'd42: begin
5'd21: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address1_w;
end
6'd43: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
end
end
6'd44: begin
5'd22: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
end
end
6'd45: begin
5'd23: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata3_w;
end
6'd46: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata2_w;
end
6'd47: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata1_w;
end
6'd48: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
end
end
6'd49: begin
5'd24: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata3_w;
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
end
6'd50: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata2_w;
end
6'd51: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata1_w;
end
6'd52: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata0_w;
end
end
endcase
endcase
end
end
@ -12938,112 +12630,64 @@ always @(posedge sys_clk) begin
litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
end
end
litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
if (csrbank1_dfii_pi0_address1_re) begin
litedramcore_phaseinjector0_address_storage[13:8] <= csrbank1_dfii_pi0_address1_r;
end
if (csrbank1_dfii_pi0_address0_re) begin
if (csrbank1_dfii_pi0_address0_re) begin
litedramcore_phaseinjector0_address_storage[7:0] <= csrbank1_dfii_pi0_address0_r;
litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
end
end
litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
if (csrbank1_dfii_pi0_baddress0_re) begin
if (csrbank1_dfii_pi0_baddress0_re) begin
litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
end
end
litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
if (csrbank1_dfii_pi0_wrdata3_re) begin
litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank1_dfii_pi0_wrdata3_r;
end
if (csrbank1_dfii_pi0_wrdata2_re) begin
litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank1_dfii_pi0_wrdata2_r;
end
if (csrbank1_dfii_pi0_wrdata1_re) begin
litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank1_dfii_pi0_wrdata1_r;
end
if (csrbank1_dfii_pi0_wrdata0_re) begin
if (csrbank1_dfii_pi0_wrdata0_re) begin
litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank1_dfii_pi0_wrdata0_r;
litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
end
end
litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
if (csrbank1_dfii_pi1_command0_re) begin
if (csrbank1_dfii_pi1_command0_re) begin
litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
end
end
litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
if (csrbank1_dfii_pi1_address1_re) begin
litedramcore_phaseinjector1_address_storage[13:8] <= csrbank1_dfii_pi1_address1_r;
end
if (csrbank1_dfii_pi1_address0_re) begin
if (csrbank1_dfii_pi1_address0_re) begin
litedramcore_phaseinjector1_address_storage[7:0] <= csrbank1_dfii_pi1_address0_r;
litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
end
end
litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
if (csrbank1_dfii_pi1_baddress0_re) begin
if (csrbank1_dfii_pi1_baddress0_re) begin
litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
end
end
litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
if (csrbank1_dfii_pi1_wrdata3_re) begin
litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank1_dfii_pi1_wrdata3_r;
end
if (csrbank1_dfii_pi1_wrdata2_re) begin
litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank1_dfii_pi1_wrdata2_r;
end
if (csrbank1_dfii_pi1_wrdata1_re) begin
litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank1_dfii_pi1_wrdata1_r;
end
if (csrbank1_dfii_pi1_wrdata0_re) begin
if (csrbank1_dfii_pi1_wrdata0_re) begin
litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank1_dfii_pi1_wrdata0_r;
litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
end
end
litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
if (csrbank1_dfii_pi2_command0_re) begin
if (csrbank1_dfii_pi2_command0_re) begin
litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
end
end
litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
if (csrbank1_dfii_pi2_address1_re) begin
litedramcore_phaseinjector2_address_storage[13:8] <= csrbank1_dfii_pi2_address1_r;
end
if (csrbank1_dfii_pi2_address0_re) begin
if (csrbank1_dfii_pi2_address0_re) begin
litedramcore_phaseinjector2_address_storage[7:0] <= csrbank1_dfii_pi2_address0_r;
litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
end
end
litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
if (csrbank1_dfii_pi2_baddress0_re) begin
if (csrbank1_dfii_pi2_baddress0_re) begin
litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
end
end
litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
if (csrbank1_dfii_pi2_wrdata3_re) begin
litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank1_dfii_pi2_wrdata3_r;
end
if (csrbank1_dfii_pi2_wrdata2_re) begin
litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank1_dfii_pi2_wrdata2_r;
end
if (csrbank1_dfii_pi2_wrdata1_re) begin
litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank1_dfii_pi2_wrdata1_r;
end
if (csrbank1_dfii_pi2_wrdata0_re) begin
if (csrbank1_dfii_pi2_wrdata0_re) begin
litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank1_dfii_pi2_wrdata0_r;
litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
end
end
litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
if (csrbank1_dfii_pi3_command0_re) begin
if (csrbank1_dfii_pi3_command0_re) begin
litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
end
end
litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
if (csrbank1_dfii_pi3_address1_re) begin
litedramcore_phaseinjector3_address_storage[13:8] <= csrbank1_dfii_pi3_address1_r;
end
if (csrbank1_dfii_pi3_address0_re) begin
if (csrbank1_dfii_pi3_address0_re) begin
litedramcore_phaseinjector3_address_storage[7:0] <= csrbank1_dfii_pi3_address0_r;
litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
end
end
litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
if (csrbank1_dfii_pi3_baddress0_re) begin
if (csrbank1_dfii_pi3_baddress0_re) begin
litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
end
end
litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
if (csrbank1_dfii_pi3_wrdata3_re) begin
litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank1_dfii_pi3_wrdata3_r;
end
if (csrbank1_dfii_pi3_wrdata2_re) begin
litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank1_dfii_pi3_wrdata2_r;
end
if (csrbank1_dfii_pi3_wrdata1_re) begin
litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank1_dfii_pi3_wrdata1_r;
end
if (csrbank1_dfii_pi3_wrdata0_re) begin
if (csrbank1_dfii_pi3_wrdata0_re) begin
litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank1_dfii_pi3_wrdata0_r;
litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
end
end
litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
if (sys_rst) begin
if (sys_rst) begin
Benjamin Herrenschmidt
5 years ago