litedram: disable block_until_ready, regenerate

Recent litedram gets stuck at memtest unless block_until_ready=False.
(discussion in https://github.com/enjoy-digital/litedram/pull/292)

This change regenerates with latest litedram and litex
62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.")
add2746a ("tools/litex_cli: Rename wb to bus.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
fpu-constant
Matt Johnston 3 years ago
parent 67164a6ffa
commit 5a3cdc8b22

@ -31,6 +31,7 @@
"user_ports": {
"native_0": {
"type": "native",
"block_until_ready": False,
},
},
}

@ -31,6 +31,7 @@
"user_ports": {
"native_0": {
"type": "native",
"block_until_ready": False,
},
},
}

@ -31,6 +31,7 @@
"user_ports": {
"native_0": {
"type": "native",
"block_until_ready": False,
},
},
}

@ -31,6 +31,7 @@
"user_ports": {
"native_0": {
"type": "native",
"block_until_ready": False,
},
},
}

@ -31,6 +31,7 @@
"user_ports": {
"native_0": {
"type": "native",
"block_until_ready": False,
},
},
}

@ -31,6 +31,7 @@
"user_ports": {
"native_0": {
"type": "native",
"block_until_ready": False,
},
},
}

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@ -100,7 +100,7 @@ begin
if rising_edge(clk) then
oack <= '0';
if (wb_in.cyc and wb_in.stb) = '1' then
adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS - 3 downto 0))));
if wb_in.we = '0' then
obuf <= init_ram(adr);
else

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