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@ -384,9 +384,9 @@ begin
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if r.store_tag(TAG_BITS - 1) = '0' then
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if r.store_tag(TAG_BITS - 1) = '0' then
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wr_dat <= wishbone_in.dat;
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wr_dat <= wishbone_in.dat;
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else
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else
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for i in 0 to (wishbone_in.dat'length / 8) - 1 loop
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for ii in 0 to (wishbone_in.dat'length / 8) - 1 loop
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j := ((i / 4) * 4) + (3 - (i mod 4));
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j := ((ii / 4) * 4) + (3 - (ii mod 4));
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wr_dat(i * 8 + 7 downto i * 8) <= wishbone_in.dat(j * 8 + 7 downto j * 8);
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wr_dat(ii * 8 + 7 downto ii * 8) <= wishbone_in.dat(j * 8 + 7 downto j * 8);
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end loop;
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end loop;
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end if;
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end if;
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do_read <= not (stall_in or use_previous);
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do_read <= not (stall_in or use_previous);
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@ -397,8 +397,8 @@ begin
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cache_out(i) <= dout;
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cache_out(i) <= dout;
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rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
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rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
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wr_addr <= std_ulogic_vector(to_unsigned(r.store_row, ROW_BITS));
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wr_addr <= std_ulogic_vector(to_unsigned(r.store_row, ROW_BITS));
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for i in 0 to ROW_SIZE-1 loop
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for ii in 0 to ROW_SIZE-1 loop
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wr_sel(i) <= do_write;
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wr_sel(ii) <= do_write;
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end loop;
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end loop;
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end process;
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end process;
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end generate;
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end generate;
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