SOC memory wishbone should clear ACK regardless of STB

The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

fpga/mw_soc_memory.vhdl

@@ -92,10 +92,8 @@ begin
 			    state <= ACK;
 			end if;
 		    when ACK =>
-			if wishbone_in.stb = '0' then
+			read_ack <= '0';
-			    read_ack <= '0';
+			state <= IDLE;
-			    state <= IDLE;
-			end if;
 		    end case;
 		else
 		    state <= IDLE;