Reduce wishbone address size to 32-bit

For now ... it reduces the routing pressure on the FPGA

This needs manual adjustment of the address decoder in soc.vhdl, at
least until I can figure out how to deal with std_match

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

# Conflicts:
#	soc.vhdl

# Conflicts:
#	soc.vhdl
jtag-port
Benjamin Herrenschmidt 5 years ago
parent 1a63c39704
commit 6dd0b514ac

@ -111,11 +111,11 @@ begin
SLAVE_NONE); SLAVE_NONE);
variable slave : slave_type; variable slave : slave_type;
begin begin
-- Simple address decoder -- Simple address decoder.
slave := SLAVE_NONE; slave := SLAVE_NONE;
if wb_master_out.adr(63 downto 24) = x"0000000000" then if wb_master_out.adr(31 downto 24) = x"00" then
slave := SLAVE_MEMORY; slave := SLAVE_MEMORY;
elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then elsif wb_master_out.adr(31 downto 24) = x"c0" then
if wb_master_out.adr(23 downto 12) = x"002" then if wb_master_out.adr(23 downto 12) = x"002" then
slave := SLAVE_UART_0; slave := SLAVE_UART_0;
end if; end if;

@ -2,7 +2,7 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;


package wishbone_types is package wishbone_types is
constant wishbone_addr_bits : integer := 64; constant wishbone_addr_bits : integer := 32;
constant wishbone_data_bits : integer := 64; constant wishbone_data_bits : integer := 64;
constant wishbone_sel_bits : integer := wishbone_data_bits/8; constant wishbone_sel_bits : integer := wishbone_data_bits/8;



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