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@ -81,7 +81,8 @@ entity soc is
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DCACHE_TLB_SET_SIZE : natural := 64;
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DCACHE_TLB_NUM_WAYS : natural := 2;
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HAS_SD_CARD : boolean := false;
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NGPIO : natural := 0
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HAS_GPIO : boolean := false;
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NGPIO : natural := 32
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);
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port(
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rst : in std_ulogic;
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@ -913,20 +914,22 @@ begin
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icp_out => ics_to_icp
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);
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gpio : entity work.gpio
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generic map(
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NGPIO => NGPIO
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)
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port map(
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clk => system_clk,
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rst => rst_gpio,
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wb_in => wb_gpio_in,
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wb_out => wb_gpio_out,
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gpio_in => gpio_in,
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gpio_out => gpio_out,
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gpio_dir => gpio_dir,
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intr => gpio_intr
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);
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gpio0_gen: if HAS_GPIO generate
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gpio : entity work.gpio
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generic map(
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NGPIO => NGPIO
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)
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port map(
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clk => system_clk,
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rst => rst_gpio,
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wb_in => wb_gpio_in,
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wb_out => wb_gpio_out,
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gpio_in => gpio_in,
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gpio_out => gpio_out,
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gpio_dir => gpio_dir,
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intr => gpio_intr
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);
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end generate;
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-- Assign external interrupts
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interrupts: process(all)
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