Remove -add from xdc files

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
remove-potato-uart
Anton Blanchard 3 years ago committed by Anton Blanchard
parent 187199c489
commit 75e06a1e30

@ -531,7 +531,7 @@ set_property CONFIG_MODE SPIx4 [current_design]
# Clock constraints # Clock constraints
################################################################################ ################################################################################


create_clock -add -name sys_clk_pin -period 10.00 [get_ports { ext_clk }]; create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];


create_clock -name eth_rx_clk -period 40.0 [get_ports { eth_clocks_rx }] create_clock -name eth_rx_clk -period 40.0 [get_ports { eth_clocks_rx }]



@ -1,6 +1,6 @@
## Clock signal 12 MHz ## Clock signal 12 MHz
set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }]; set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
create_clock -add -name sys_clk_pin -period 83.33 [get_ports {ext_clk}]; create_clock -name sys_clk_pin -period 83.33 [get_ports {ext_clk}];


set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }]; set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }]; set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];

@ -313,7 +313,7 @@ set_property CONFIG_MODE SPIx4 [current_design]
# Clock constraints # Clock constraints
################################################################################ ################################################################################


create_clock -add -name sys_clk_pin -period 10.00 [get_ports { ext_clk }]; create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];


################################################################################ ################################################################################
# False path constraints (from LiteX as they relate to LiteDRAM) # False path constraints (from LiteX as they relate to LiteDRAM)

@ -1,5 +1,5 @@
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports ext_clk] set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports ext_clk]
create_clock -period 10.000 -name sys_clk_pin -add [get_ports ext_clk] create_clock -period 10.000 -name sys_clk_pin [get_ports ext_clk]


set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports ext_rst] set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports ext_rst]



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