Merge pull request #254 from antonblanchard/fix-verilator

Add verilator FPGA target
jtag-port
Anton Blanchard 4 years ago committed by GitHub
commit 86bdfe6fd4
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@ -177,6 +177,13 @@ clkgen=fpga/clk_gen_ecp5.vhd
toplevel=fpga/top-generic.vhdl toplevel=fpga/top-generic.vhdl
dmi_dtm=dmi_dtm_dummy.vhdl dmi_dtm=dmi_dtm_dummy.vhdl


ifeq ($(FPGA_TARGET), verilator)
RESET_LOW=true
CLK_INPUT=50000000
CLK_FREQUENCY=50000000
clkgen=fpga/clk_gen_bypass.vhd
endif

fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \ fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \ fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
nonrandom.vhdl nonrandom.vhdl

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