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@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
@@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
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end entity wishbone_bram_wrapper; |
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architecture behaviour of wishbone_bram_wrapper is |
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constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3; |
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constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3; |
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-- RAM interface |
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signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0); |
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