Merge pull request #360 from antonblanchard/log2ceil-issue

wishbone_bram_wrapper ram_addr_bits is 1 bit off
alt-reset-address
Michael Neuling 2 years ago committed by GitHub
commit 8bf48ac094
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@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
end entity wishbone_bram_wrapper;

architecture behaviour of wishbone_bram_wrapper is
constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3;

-- RAM interface
signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);

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