@ -80,6 +80,7 @@ architecture behave of core is
signal complete: std_ulogic;
signal complete: std_ulogic;
signal terminate: std_ulogic;
signal terminate: std_ulogic;
signal core_rst: std_ulogic;
signal core_rst: std_ulogic;
signal icache_rst: std_ulogic;
-- Debug actions
-- Debug actions
signal dbg_core_stop: std_ulogic;
signal dbg_core_stop: std_ulogic;
@ -134,13 +135,15 @@ begin
)
)
port map(
port map(
clk => clk,
clk => clk,
rst => rst or dbg_icache_rst,
rst => icache_rst,
i_in => fetch2_to_icache,
i_in => fetch2_to_icache,
i_out => icache_to_fetch2,
i_out => icache_to_fetch2,
wishbone_out => wishbone_insn_out,
wishbone_out => wishbone_insn_out,
wishbone_in => wishbone_insn_in
wishbone_in => wishbone_insn_in
);
);
icache_rst <= rst or dbg_icache_rst;
decode1_0: entity work.decode1
decode1_0: entity work.decode1
port map (
port map (
clk => clk,
clk => clk,