Add a script to post process the microwatt verilog for caravel

caravel/insert_power.py

@@ -0,0 +1,70 @@
+#!/usr/bin/python
+
+import sys
+import re
+
+module_regex = r'[a-zA-Z0-9_\.\\]+'
+
+# match:
+# module dcache(clk, rst, d_in, m_in, wishbone_in, d_out, m_out, stall_out, wishbone_out);
+module_re = re.compile(r'module\s+(' + module_regex + r')\((.*)\);')
+
+# match:
+# dcache_64_2_2_2_2_12_0 dcache_0 (
+hookup_re = re.compile(r'\s+(' + module_regex + r') ' + module_regex + r'\s+\(')
+
+header1 = """\
+`ifdef USE_POWER_PINS
+        vdda1, vdda2, vssa1, vssa2, vccd1, vccd2, vssd1, vssd2,
+`endif\
+"""
+
+header2 = """\
+`ifdef USE_POWER_PINS
+  inout vdda1;        // User area 1 3.3V supply
+  inout vdda2;        // User area 2 3.3V supply
+  inout vssa1;        // User area 1 analog ground
+  inout vssa2;        // User area 2 analog ground
+  inout vccd1;        // User area 1 1.8V supply
+  inout vccd2;        // User area 2 1.8v supply
+  inout vssd1;        // User area 1 digital ground
+  inout vssd2;        // User area 2 digital ground
+`endif\
+"""
+
+header3 = """\
+`ifdef USE_POWER_PINS
+    .vdda1(vdda1),  // User area 1 3.3V power
+    .vdda2(vdda2),  // User area 2 3.3V power
+    .vssa1(vssa1),  // User area 1 analog ground
+    .vssa2(vssa2),  // User area 2 analog ground
+    .vccd1(vccd1),  // User area 1 1.8V power
+    .vccd2(vccd2),  // User area 2 1.8V power
+    .vssd1(vssd1),  // User area 1 digital ground
+    .vssd2(vssd2),  // User area 2 digital ground
+`endif\
+"""
+
+if len(sys.argv) < 3:
+    print("Usage: insert_power.py verilog.v module1 module2..")
+    sys.exit(1);
+
+verilog_file = sys.argv[1]
+modules = sys.argv[2:]
+
+with open(sys.argv[1]) as f:
+    for line in f:
+        m = module_re.match(line)
+        m2 = hookup_re.match(line)
+        if m and m.group(1) in modules:
+            module_name = m.group(1)
+            module_args = m.group(2)
+            print('module %s(' % module_name)
+            print(header1)
+            print(' %s);' % module_args)
+            print(header2)
+        elif m2 and m2.group(1) in modules:
+            print(line, end='')
+            print(header3)
+        else:
+            print(line, end='')

caravel/process-microwatt-verilog.sh

@@ -0,0 +1,54 @@
+#!/bin/bash -e
+
+# process microwatt verilog
+
+FILE=microwatt.v
+
+# Remove these modules that are implemented as hard macros
+for module in register_file_0_1489f923c4dca729178b3e3233458550d8dddf29 dcache_64_2_2_2_2_12_0 icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f cache_ram_4_64_1489f923c4dca729178b3e3233458550d8dddf29 cache_ram_4_64_3f29546453678b855931c174a97d6c0894b8f546 plru_1 multiply_4
+do
+        sed -i "/^module $module/,/^endmodule/d" $FILE
+done
+
+# Remove the debug bus in the places we call our macros
+for module in dcache_64_2_2_2_2_12_0 icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f register_file_0_1489f923c4dca729178b3e3233458550d8dddf29; do
+	for port in dbg_gpr log_out sim_dump; do
+		sed -i "/  $module /,/);/{ /$port/d }" $FILE
+	done
+done
+
+# Rename these modules to match the hard macro names
+sed -i 's/register_file_0_1489f923c4dca729178b3e3233458550d8dddf29/register_file/' $FILE
+sed -i 's/dcache_64_2_2_2_2_12_0/dcache/' $FILE
+sed -i 's/icache_64_8_2_2_4_12_56_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f/icache/' $FILE
+sed -i 's/toplevel/microwatt/' $FILE
+
+# Add power to all macros, and route power in microwatt down to them
+caravel/insert_power.py $FILE dcache icache register_file multiply_4 RAM_512x64 main_bram_64_10_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 soc_4096_50000000_0_0_4_0_4_0_c832069ef22b63469d396707bc38511cc2410ddb wishbone_bram_wrapper_4096_a75adb9e07879fb6c63b494abe06e3f9a6bb2ed9 microwatt core_0_602f7ae323a872754ff5ac989c2e00f60e206d8e execute1_0_0e356ba505631fbf715758bed27d503f8b260e3a > $FILE.tmp && mv $FILE.tmp $FILE
+
+# Add defines
+sed -i '1 a\
+\
+/* Hard macros */\
+`ifdef SIM\
+`include "RAM_512x64.v"\
+`include "register_file.v"\
+`include "icache.v"\
+`include "dcache.v"\
+`include "multiply_4.v"\
+`endif\
+\
+/* JTAG */\
+`include "tap_top.v"\
+\
+/* UART */\
+`include "raminfr.v"\
+`include "uart_receiver.v"\
+`include "uart_rfifo.v"\
+`include "uart_tfifo.v"\
+`include "uart_transmitter.v"\
+`include "uart_defines.v"\
+`include "uart_regs.v"\
+`include "uart_sync_flops.v"\
+`include "uart_wb.v"\
+`include "uart_top.v"' $FILE