wishbone_debug_master: Improve timing

The current code has the possibility that we could set reg_addr
or reg_ctrl and then increment reg_addr in the same cycle, resulting
in some long timing paths.  Rearrange the code to make it clear
that we are not trying to add an auto-increment to data from
outside the module; in any given cycle we either set one of
reg_addr and reg_ctrl, or we possibly increment reg_addr.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

wishbone_debug_master.vhdl

@@ -90,9 +90,8 @@ begin
 		    elsif dmi_addr = DBG_WB_CTRL then
 			reg_ctrl <= dmi_din(10 downto 0);
 		    end if;
-		end if;
+                elsif state = WB_CYCLE and (wb_in.ack and reg_ctrl(8))= '1'  then
-		-- Address register auto-increment
+		    -- Address register auto-increment
-		if state = WB_CYCLE and (wb_in.ack and reg_ctrl(8))= '1'  then
 		    reg_addr <= std_ulogic_vector(unsigned(reg_addr) +
 						  decode_autoinc(reg_ctrl(10 downto 9)));
 		end if;