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Merge pull request #60 from antonblanchard/testbenches

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Add a few more test benches
jtag-port
Anton Blanchard 5 years ago committed by GitHub
parent d573748da0 1b6eef2a5d
commit a4c8dd860a
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3 changed files with 160 additions and 33 deletions
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9
Makefile
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@ -2,7 +2,7 @@ GHDL=ghdl
GHDLFLAGS=--std=08
CFLAGS=-O2 -Wall

all = core_tb simple_ram_behavioural_tb soc_reset_tb
all = core_tb simple_ram_behavioural_tb soc_reset_tb icache_tb multiply_tb
# XXX
# loadstore_tb fetch_tb

@ -27,6 +27,7 @@ glibc_random_helpers.o:
glibc_random.o: glibc_random_helpers.o
helpers.o:
icache.o: common.o wishbone_types.o
icache_tb.o: common.o wishbone_types.o icache.o simple_ram_behavioural.o
insn_helpers.o:
loadstore1.o: common.o
loadstore2.o: common.o helpers.o wishbone_types.o
@ -54,9 +55,15 @@ core_tb: core_tb.o simple_ram_behavioural_helpers_c.o sim_console_c.o
fetch_tb: fetch_tb.o
$(GHDL) -e $(GHDLFLAGS) $@

icache_tb: icache_tb.o
$(GHDL) -e $(GHDLFLAGS) -Wl,simple_ram_behavioural_helpers_c.o $@

loadstore_tb: loadstore_tb.o
$(GHDL) -e $(GHDLFLAGS) $@

multiply_tb: multiply_tb.o
$(GHDL) -e $(GHDLFLAGS) $@

simple_ram_tb: simple_ram_tb.o
$(GHDL) -e $(GHDLFLAGS) $@


120
icache_tb.vhdl
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@ -0,0 +1,120 @@
library ieee;
use ieee.std_logic_1164.all;

library work;
use work.common.all;
use work.wishbone_types.all;

entity icache_tb is
end icache_tb;

architecture behave of icache_tb is
signal clk : std_ulogic;
signal rst : std_ulogic;

signal i_out : Fetch2ToIcacheType;
signal i_in : IcacheToFetch2Type;

signal wb_bram_in : wishbone_master_out;
signal wb_bram_out : wishbone_slave_out;

constant clk_period : time := 10 ns;
begin
icache0: entity work.icache
generic map(
LINE_SIZE_DW => 8,
NUM_LINES => 4
)
port map(
clk => clk,
rst => rst,
i_in => i_out,
i_out => i_in,
wishbone_out => wb_bram_in,
wishbone_in => wb_bram_out
);

-- BRAM Memory slave
bram0: entity work.mw_soc_memory
generic map(
MEMORY_SIZE => 128,
RAM_INIT_FILE => "icache_test.bin"
)
port map(
clk => clk,
rst => rst,
wishbone_in => wb_bram_in,
wishbone_out => wb_bram_out
);

clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

rst_process: process
begin
rst <= '1';
wait for 2*clk_period;
rst <= '0';
wait;
end process;

stim: process
begin
i_out.req <= '0';
i_out.addr <= (others => '0');

wait for 4*clk_period;

i_out.req <= '1';
i_out.addr <= x"0000000000000004";

wait for 30*clk_period;

assert i_in.ack = '1';
assert i_in.insn = x"00000001";

i_out.req <= '0';

wait for clk_period;

-- hit
i_out.req <= '1';
i_out.addr <= x"0000000000000008";
wait for clk_period/2;
assert i_in.ack = '1';
assert i_in.insn = x"00000002";
wait for clk_period/2;

-- another miss
i_out.req <= '1';
i_out.addr <= x"0000000000000040";

wait for 30*clk_period;

assert i_in.ack = '1';
assert i_in.insn = x"00000010";

-- test something that aliases
i_out.req <= '1';
i_out.addr <= x"0000000000000100";
wait for clk_period/2;
assert i_in.ack = '0';
wait for clk_period/2;

wait for 30*clk_period;

assert i_in.ack = '1';
assert i_in.insn = x"00000040";

i_out.req <= '0';

assert false report "end of test" severity failure;
wait;

end process;
end;

64
multiply_tb.vhdl
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@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.decode_types.all;
use work.common.all;
use work.glibc_random.all;
use work.ppc_fx_insns.all;
@ -14,9 +15,9 @@ architecture behave of multiply_tb is
signal clk : std_ulogic;
constant clk_period : time := 10 ns;

constant pipeline_depth: integer := 6;
constant pipeline_depth: integer := 4;

signal m1 : DecodeToMultiplyType;
signal m1 : Decode2ToMultiplyType;
signal m2 : MultiplyToWritebackType;
begin
multiply_0: entity work.multiply
@ -38,8 +39,7 @@ begin
wait for clk_period;

m1.valid <= '1';
m1.mul_type <= LOWER_64;
m1.nia <= (others => '0');
m1.insn_type <= OP_MUL_L64;
m1.write_reg <= "10001";
m1.data1 <= '0' & x"0000000000001000";
m1.data2 <= '0' & x"0000000000001111";
@ -58,9 +58,9 @@ begin

wait for clk_period;
assert m2.valid = '1';
assert m2.write_enable = '1';
assert m2.write_reg = "10001";
assert m2.write_data = x"0000000001111000";
assert m2.write_reg_enable = '1';
assert m2.write_reg_nr = "10001";
assert m2.write_reg_data = x"0000000001111000";
assert m2.write_cr_enable = '0';

wait for clk_period;
@ -76,11 +76,11 @@ begin

wait for clk_period * (pipeline_depth-1);
assert m2.valid = '1';
assert m2.write_enable = '1';
assert m2.write_reg = "10001";
assert m2.write_data = x"0000000001111000";
assert m2.write_reg_enable = '1';
assert m2.write_reg_nr = "10001";
assert m2.write_reg_data = x"0000000001111000";
assert m2.write_cr_enable = '1';
assert m2.cr = x"4";
assert m2.write_cr_data = x"40000000";

-- test mulld
mulld_loop : for i in 0 to 1000 loop
@ -92,7 +92,7 @@ begin
m1.data1 <= '0' & ra;
m1.data2 <= '0' & rb;
m1.valid <= '1';
m1.mul_type <= LOWER_64;
m1.insn_type <= OP_MUL_L64;

wait for clk_period;

@ -102,8 +102,8 @@ begin

assert m2.valid = '1';

assert to_hstring(behave_rt) = to_hstring(m2.write_data)
report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop;

-- test mulhdu
@ -116,7 +116,7 @@ begin
m1.data1 <= '0' & ra;
m1.data2 <= '0' & rb;
m1.valid <= '1';
m1.mul_type <= UPPER_64;
m1.insn_type <= OP_MUL_H64;

wait for clk_period;

@ -126,8 +126,8 @@ begin

assert m2.valid = '1';

assert to_hstring(behave_rt) = to_hstring(m2.write_data)
report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop;

-- test mulhd
@ -140,7 +140,7 @@ begin
m1.data1 <= ra(63) & ra;
m1.data2 <= rb(63) & rb;
m1.valid <= '1';
m1.mul_type <= UPPER_64;
m1.insn_type <= OP_MUL_H64;

wait for clk_period;

@ -150,8 +150,8 @@ begin

assert m2.valid = '1';

assert to_hstring(behave_rt) = to_hstring(m2.write_data)
report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop;

-- test mullw
@ -166,7 +166,7 @@ begin
m1.data2 <= (others => rb(31));
m1.data2(31 downto 0) <= rb(31 downto 0);
m1.valid <= '1';
m1.mul_type <= LOWER_64;
m1.insn_type <= OP_MUL_L64;

wait for clk_period;

@ -176,8 +176,8 @@ begin

assert m2.valid = '1';

assert to_hstring(behave_rt) = to_hstring(m2.write_data)
report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop;

-- test mulhw
@ -192,7 +192,7 @@ begin
m1.data2 <= (others => rb(31));
m1.data2(31 downto 0) <= rb(31 downto 0);
m1.valid <= '1';
m1.mul_type <= UPPER_32;
m1.insn_type <= OP_MUL_H32;

wait for clk_period;

@ -202,8 +202,8 @@ begin

assert m2.valid = '1';

assert to_hstring(behave_rt) = to_hstring(m2.write_data)
report "bad mulhw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulhw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop;

-- test mulhwu
@ -218,7 +218,7 @@ begin
m1.data2 <= (others => '0');
m1.data2(31 downto 0) <= rb(31 downto 0);
m1.valid <= '1';
m1.mul_type <= UPPER_32;
m1.insn_type <= OP_MUL_H32;

wait for clk_period;

@ -228,8 +228,8 @@ begin

assert m2.valid = '1';

assert to_hstring(behave_rt) = to_hstring(m2.write_data)
report "bad mulhwu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulhwu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop;

-- test mulli
@ -243,7 +243,7 @@ begin
m1.data2 <= (others => si(15));
m1.data2(15 downto 0) <= si;
m1.valid <= '1';
m1.mul_type <= LOWER_64;
m1.insn_type <= OP_MUL_L64;

wait for clk_period;

@ -253,8 +253,8 @@ begin

assert m2.valid = '1';

assert to_hstring(behave_rt) = to_hstring(m2.write_data)
report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_data);
assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
end loop;

assert false report "end of test" severity failure;

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