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@ -197,7 +197,7 @@ architecture behaviour of fpu is
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-- Each output value is the inverse of the center of the input
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-- Each output value is the inverse of the center of the input
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-- range for the value, i.e. entry 0 is 1 / (1 + 1/512),
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-- range for the value, i.e. entry 0 is 1 / (1 + 1/512),
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-- entry 1 is 1 / (1 + 3/512), etc.
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-- entry 1 is 1 / (1 + 3/512), etc.
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signal inverse_table : lookup_table := (
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constant inverse_table : lookup_table := (
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-- 1/x lookup table
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-- 1/x lookup table
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-- Unit bit is assumed to be 1, so input range is [1, 2)
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-- Unit bit is assumed to be 1, so input range is [1, 2)
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18x"3fc01", 18x"3f411", 18x"3ec31", 18x"3e460", 18x"3dc9f", 18x"3d4ec", 18x"3cd49", 18x"3c5b5",
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18x"3fc01", 18x"3f411", 18x"3ec31", 18x"3e460", 18x"3dc9f", 18x"3d4ec", 18x"3cd49", 18x"3c5b5",
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