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@ -12,8 +12,8 @@ all: $(all)
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$(GHDL) -a $(GHDLFLAGS) $<
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common.o: decode_types.o
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core_tb.o: common.o core.o soc.o
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core.o: common.o wishbone_types.o fetch1.o fetch2.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o wishbone_arbiter.o
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core_tb.o: common.o wishbone_types.o soc.o
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core.o: common.o wishbone_types.o fetch1.o fetch2.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o
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cr_file.o: common.o
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crhelpers.o: common.o
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decode1.o: common.o decode_types.o
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@ -34,15 +34,14 @@ multiply.o: common.o decode_types.o ppc_fx_insns.o crhelpers.o
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ppc_fx_insns.o: helpers.o
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register_file.o: common.o
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sim_console.o:
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sim_uart.o: sim_console.o
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simple_ram_behavioural_helpers.o:
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simple_ram_behavioural_tb.o: wishbone_types.o simple_ram_behavioural.o
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simple_ram_behavioural.o: wishbone_types.o simple_ram_behavioural_helpers.o
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sim_uart.o: wishbone_types.o sim_console.o
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soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o simple_ram_behavioural.o
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wishbone_arbiter.o: wishbone_types.o
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wishbone_types.o:
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writeback.o: common.o
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soc.o: wishbone_types.o simple_ram_behavioural.o sim_uart.o
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fpga/soc_reset_tb.o: fpga/soc_reset.o
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soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
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