soc: Don't require dram wishbones signals to be wired by toplevel

Currently, when not using litedram, the top level still has to hook
up "dummy" wishbones to the main dram and control dram busses coming
out of the SoC and provide ack signals.

Instead, make the SoC generate the acks internally when not using
litedram and use defaults to make the wiring entirely optional.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

core_flash_tb.vhdl

@@ -15,12 +15,6 @@ architecture behave of core_flash_tb is
 	-- testbench signals
 	constant clk_period : time := 10 ns;
 
-        -- Dummy DRAM
-	signal wb_dram_in : wishbone_master_out;
-	signal wb_dram_out : wishbone_slave_out;
-	signal wb_dram_ctrl_in : wb_io_master_out;
-	signal wb_dram_ctrl_out : wb_io_slave_out;
-
         -- SPI
         signal spi_sck     : std_ulogic;
         signal spi_cs_n    : std_ulogic := '1';
@@ -46,10 +40,6 @@ begin
 	port map(
 	    rst => rst,
 	    system_clk => clk,
-	    wb_dram_in => wb_dram_in,
-	    wb_dram_out => wb_dram_out,
-	    wb_dram_ctrl_in => wb_dram_ctrl_in,
-	    wb_dram_ctrl_out => wb_dram_ctrl_out,
             spi_flash_sck     => spi_sck,
             spi_flash_cs_n    => spi_cs_n,
             spi_flash_sdat_o  => spi_sdat_o,
@@ -104,12 +94,4 @@ begin
 
     jtag: entity work.sim_jtag;
 
-    -- Dummy DRAM
-    wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
-    wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
-    wb_dram_out.stall <= '0';
-    wb_dram_ctrl_out.ack <= wb_dram_ctrl_in.cyc and wb_dram_ctrl_in.stb;
-    wb_dram_ctrl_out.dat <= x"FFFFFFFF";
-    wb_dram_ctrl_out.stall <= '0';
-
 end;

core_tb.vhdl

@@ -14,12 +14,6 @@ architecture behave of core_tb is
 
 	-- testbench signals
 	constant clk_period : time := 10 ns;
-
-        -- Dummy DRAM
-	signal wb_dram_in : wishbone_master_out;
-	signal wb_dram_out : wishbone_slave_out;
-	signal wb_dram_ctrl_in : wb_io_master_out;
-	signal wb_dram_ctrl_out : wb_io_slave_out;
 begin
 
     soc0: entity work.soc
@@ -31,11 +25,7 @@ begin
 	    )
 	port map(
 	    rst => rst,
-	    system_clk => clk,
-	    wb_dram_in => wb_dram_in,
-	    wb_dram_out => wb_dram_out,
-	    wb_dram_ctrl_in => wb_dram_ctrl_in,
-	    wb_dram_ctrl_out => wb_dram_ctrl_out
+	    system_clk => clk
 	    );
 
     clk_process: process
@@ -56,12 +46,4 @@ begin
 
     jtag: entity work.sim_jtag;
 
-    -- Dummy DRAM
-    wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
-    wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
-    wb_dram_out.stall <= '0';
-    wb_dram_ctrl_out.ack <= wb_dram_ctrl_in.cyc and wb_dram_ctrl_in.stb;
-    wb_dram_ctrl_out.dat <= x"FFFFFFFF";
-    wb_dram_ctrl_out.stall <= '0';
-
 end;

fpga/top-generic.vhdl

@@ -33,14 +33,6 @@ architecture behaviour of toplevel is
     signal system_clk : std_ulogic;
     signal system_clk_locked : std_ulogic;
 
-    -- DRAM main data wishbone connection
-    signal wb_dram_in       : wishbone_master_out;
-    signal wb_dram_out      : wishbone_slave_out;
-
-    -- DRAM control wishbone connection
-    signal wb_dram_ctrl_in  : wb_io_master_out;
-    signal wb_dram_ctrl_out : wb_io_slave_out;
-
 begin
 
     reset_controller: entity work.soc_reset
@@ -81,19 +73,7 @@ begin
 	    system_clk        => system_clk,
 	    rst               => soc_rst,
 	    uart0_txd         => uart0_txd,
-	    uart0_rxd         => uart0_rxd,
-	    wb_dram_in        => wb_dram_in,
-	    wb_dram_out       => wb_dram_out,
-	    wb_dram_ctrl_in   => wb_dram_ctrl_in,
-	    wb_dram_ctrl_out  => wb_dram_ctrl_out
+	    uart0_rxd         => uart0_rxd
 	    );
 
-    -- Dummy DRAM
-    wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
-    wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
-    wb_dram_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack;
-    wb_dram_ctrl_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
-    wb_dram_ctrl_out.dat <= x"FFFFFFFF";
-    wb_dram_ctrl_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack;
-
 end architecture behaviour;

soc.vhdl

@@ -48,9 +48,9 @@ entity soc is
 
 	-- DRAM controller signals
 	wb_dram_in       : out wishbone_master_out;
-	wb_dram_out      : in wishbone_slave_out;
+	wb_dram_out      : in wishbone_slave_out := wishbone_slave_out_init;
 	wb_dram_ctrl_in  : out wb_io_master_out;
-	wb_dram_ctrl_out : in wb_io_slave_out;
+	wb_dram_ctrl_out : in wb_io_slave_out := wb_io_slave_out_init;
 	wb_dram_is_csr   : out std_ulogic;
 	wb_dram_is_init  : out std_ulogic;
 
@@ -267,8 +267,14 @@ begin
 	    wb_bram_in.cyc <= wb_master_out.cyc;
 	    wb_master_in <= wb_bram_out;
 	when SLAVE_TOP_DRAM =>
+            if HAS_DRAM then
                 wb_dram_in.cyc <= wb_master_out.cyc;
                 wb_master_in <= wb_dram_out;
+            else
+                wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
+                wb_master_in.dat <= (others => '1');
+                wb_master_in.stall <= '0';
+            end if;
 	when SLAVE_TOP_IO =>
 	    wb_io_in.cyc <= wb_master_out.cyc;
 	    wb_master_in <= wb_io_out;
@@ -468,12 +474,24 @@ begin
 
 	case slave_io is
 	when SLAVE_IO_DRAM_INIT =>
+            if HAS_DRAM then
                 wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
                 wb_sio_in <= wb_dram_ctrl_out;
+            else
+                wb_sio_in.ack <= wb_sio_out.cyc and wb_sio_out.stb;
+                wb_sio_in.dat <= (others => '1');
+                wb_sio_in.stall <= '0';
+            end if;
 	    wb_dram_is_init <= '1';
 	when SLAVE_IO_DRAM_CSR =>
+            if HAS_DRAM then
                 wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
                 wb_sio_in <= wb_dram_ctrl_out;
+            else
+                wb_sio_in.ack <= wb_sio_out.cyc and wb_sio_out.stb;
+                wb_sio_in.dat <= (others => '1');
+                wb_sio_in.stall <= '0';
+            end if;
 	    wb_dram_is_csr <= '1';
 	when SLAVE_IO_SYSCON =>
 	    wb_syscon_in.cyc <= wb_sio_out.cyc;

wishbone_types.vhdl

@@ -50,5 +50,5 @@ package wishbone_types is
         ack   : std_ulogic;
         stall : std_ulogic;
     end record;
-    
+    constant wb_io_slave_out_init : wb_io_slave_out := (ack => '0', stall => '0', others => (others => '0'));
 end package wishbone_types;