wb_debug: Add wishbone pipelining support

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
jtag-port
Benjamin Herrenschmidt 5 years ago
parent 3df018cdc0
commit c22734d0d9

@ -124,7 +124,6 @@ begin


-- We always move WB cyc and stb simultaneously (no pipelining yet...) -- We always move WB cyc and stb simultaneously (no pipelining yet...)
wb_out.cyc <= '1' when state = WB_CYCLE else '0'; wb_out.cyc <= '1' when state = WB_CYCLE else '0';
wb_out.stb <= '1' when state = WB_CYCLE else '0';


-- Data latch. WB will take the read data away as soon as the cycle -- Data latch. WB will take the read data away as soon as the cycle
-- terminates but we must maintain it on DMI until req goes down, so -- terminates but we must maintain it on DMI until req goes down, so
@ -145,14 +144,23 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
if (rst) then if (rst) then
state <= IDLE; state <= IDLE;
wb_out.stb <= '0';
else else
case state is case state is
when IDLE => when IDLE =>
if dmi_req = '1' and dmi_addr = DBG_WB_DATA then if dmi_req = '1' and dmi_addr = DBG_WB_DATA then
state <= WB_CYCLE; state <= WB_CYCLE;
wb_out.stb <= '1';
end if; end if;
when WB_CYCLE => when WB_CYCLE =>
if wb_in.stall = '0' then
wb_out.stb <= '0';
end if;
if wb_in.ack then if wb_in.ack then
-- We shouldn't get the ack if we hadn't already cleared
-- stb above but if this happen, don't leave it dangling.
--
wb_out.stb <= '0';
state <= DMI_WAIT; state <= DMI_WAIT;
end if; end if;
when DMI_WAIT => when DMI_WAIT =>

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