Move wishbone arbiter out of the core

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
nia-debug
Benjamin Herrenschmidt 5 years ago
parent 310a56c076
commit c97b080d8c

@ -14,8 +14,11 @@ entity core is
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;


wishbone_in : in wishbone_slave_out; wishbone_insn_in : in wishbone_slave_out;
wishbone_out : out wishbone_master_out; wishbone_insn_out : out wishbone_master_out;

wishbone_data_in : in wishbone_slave_out;
wishbone_data_out : out wishbone_master_out;


-- Added for debug, ghdl doesn't support external names unfortunately -- Added for debug, ghdl doesn't support external names unfortunately
registers : out regfile; registers : out regfile;
@ -56,12 +59,6 @@ architecture behave of core is
signal decode2_to_multiply: Decode2ToMultiplyType; signal decode2_to_multiply: Decode2ToMultiplyType;
signal multiply_to_writeback: MultiplyToWritebackType; signal multiply_to_writeback: MultiplyToWritebackType;


-- wishbone signals
signal wishbone_data_in : wishbone_slave_out;
signal wishbone_data_out : wishbone_master_out;
signal wishbone_insn_in : wishbone_slave_out;
signal wishbone_insn_out : wishbone_master_out;

-- local signals -- local signals
signal fetch_enable: std_ulogic := '0'; signal fetch_enable: std_ulogic := '0';
signal complete: std_ulogic; signal complete: std_ulogic;
@ -124,11 +121,6 @@ begin
m_in => multiply_to_writeback, w_out => writeback_to_register_file, m_in => multiply_to_writeback, w_out => writeback_to_register_file,
c_out => writeback_to_cr_file, complete_out => complete); c_out => writeback_to_cr_file, complete_out => complete);


wishbone_arbiter_0: entity work.wishbone_arbiter
port map (clk => clk, rst => rst, wb1_in => wishbone_data_out, wb1_out => wishbone_data_in,
wb2_in => wishbone_insn_out, wb2_out => wishbone_insn_in, wb_out => wishbone_out,
wb_in => wishbone_in);

-- Only single issue until we add bypass support -- Only single issue until we add bypass support
single_issue_0: process(clk) single_issue_0: process(clk)
begin begin

@ -13,6 +13,12 @@ end core_tb;
architecture behave of core_tb is architecture behave of core_tb is
signal clk, rst: std_logic; signal clk, rst: std_logic;


signal wishbone_dcore_in : wishbone_slave_out;
signal wishbone_dcore_out : wishbone_master_out;

signal wishbone_icore_in : wishbone_slave_out;
signal wishbone_icore_out : wishbone_master_out;

signal wishbone_core_in : wishbone_slave_out; signal wishbone_core_in : wishbone_slave_out;
signal wishbone_core_out : wishbone_master_out; signal wishbone_core_out : wishbone_master_out;


@ -30,8 +36,12 @@ architecture behave of core_tb is
begin begin
core_0: entity work.core core_0: entity work.core
generic map (SIM => true) generic map (SIM => true)
port map (clk => clk, rst => rst, wishbone_in => wishbone_core_in, port map (clk => clk, rst => rst,
wishbone_out => wishbone_core_out, registers => registers, terminate_out => terminate); wishbone_insn_in => wishbone_icore_in,
wishbone_insn_out => wishbone_icore_out,
wishbone_data_in => wishbone_dcore_in,
wishbone_data_out => wishbone_dcore_out,
registers => registers, terminate_out => terminate);


simple_ram_0: entity work.simple_ram_behavioural simple_ram_0: entity work.simple_ram_behavioural
generic map ( filename => "simple_ram_behavioural.bin", size => 524288) generic map ( filename => "simple_ram_behavioural.bin", size => 524288)
@ -41,6 +51,12 @@ begin
port map ( clk => clk, reset => rst, wishbone_in => wishbone_uart_out, wishbone_out => wishbone_uart_in); port map ( clk => clk, reset => rst, wishbone_in => wishbone_uart_out, wishbone_out => wishbone_uart_in);




wishbone_arbiter_0: entity work.wishbone_arbiter
port map (clk => clk, rst => rst,
wb1_in => wishbone_dcore_out, wb1_out => wishbone_dcore_in,
wb2_in => wishbone_icore_out, wb2_out => wishbone_icore_in,
wb_out => wishbone_core_out, wb_in => wishbone_core_in);

bus_process: process(wishbone_core_out, wishbone_ram_in, wishbone_uart_in) bus_process: process(wishbone_core_out, wishbone_ram_in, wishbone_uart_in)
-- Selected slave -- Selected slave
type slave_type is (SLAVE_UART, SLAVE_MEMORY, SLAVE_NONE); type slave_type is (SLAVE_UART, SLAVE_MEMORY, SLAVE_NONE);

@ -26,9 +26,13 @@ end entity soc;


architecture behaviour of soc is architecture behaviour of soc is


-- wishbone signals: -- Wishbone master signals:
signal wishbone_proc_out: wishbone_master_out; signal wishbone_proc_out: wishbone_master_out;
signal wishbone_proc_in: wishbone_slave_out; signal wishbone_proc_in: wishbone_slave_out;
signal wishbone_dcore_in : wishbone_slave_out;
signal wishbone_dcore_out : wishbone_master_out;
signal wishbone_icore_in : wishbone_slave_out;
signal wishbone_icore_out : wishbone_master_out;


-- Processor signals: -- Processor signals:
signal processor_adr_out : std_logic_vector(63 downto 0); signal processor_adr_out : std_logic_vector(63 downto 0);
@ -128,9 +132,22 @@ begin
port map( port map(
clk => system_clk, clk => system_clk,
rst => rst, rst => rst,
wishbone_insn_in => wishbone_icore_in,
wishbone_insn_out => wishbone_icore_out,
wishbone_data_in => wishbone_dcore_in,
wishbone_data_out => wishbone_dcore_out
);


wishbone_out => wishbone_proc_out, wishbone_arbiter_0: entity work.wishbone_arbiter
wishbone_in => wishbone_proc_in port map(
clk => system_clk,
rst => rst,
wb1_in => wishbone_dcore_out,
wb1_out => wishbone_dcore_in,
wb2_in => wishbone_icore_out,
wb2_out => wishbone_icore_in,
wb_out => wishbone_proc_out,
wb_in => wishbone_proc_in
); );
processor_adr_out <= wishbone_proc_out.adr; processor_adr_out <= wishbone_proc_out.adr;
processor_dat_out <= wishbone_proc_out.dat; processor_dat_out <= wishbone_proc_out.dat;

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