Merge pull request #180 from antonblanchard/Makefile-rework

Makefile rework

Makefile

@@ -1,134 +1,134 @@
-GHDL=ghdl
+GHDL ?= ghdl
-GHDLFLAGS=--std=08 -Psim-unisim
+GHDLFLAGS=--std=08 --work=unisim
 CFLAGS=-O2 -Wall
 
+GHDLSYNTH ?= ghdl.so
+YOSYS     ?= yosys
+NEXTPNR   ?= nextpnr-ecp5
+ECPPACK   ?= ecppack
+OPENOCD   ?= openocd
+
 # We need a version of GHDL built with either the LLVM or gcc backend.
-# Fedora provides this, but other distros may not. Another option, although
+# Fedora provides this, but other distros may not. Another option is to use
-# rather slow, is to use the Docker image.
+# the Docker image.
-#
+DOCKER ?= 0
-# Uncomment one of these to build with Docker or podman
+PODMAN ?= 0
-#DOCKER=docker
+
-#DOCKER=podman
+ifeq ($(DOCKER), 1)
-#
+DOCKERBIN=docker
-# Uncomment these lines to build with Docker/podman
+USE_DOCKER=1
-#PWD = $(shell pwd)
+endif
-#DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
+
-#GHDL = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
+ifeq ($(PODMAN), 1)
-#CC = $(DOCKER) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
+DOCKERBIN=podman
-
+USE_DOCKER=1
-all = core_tb soc_reset_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
+endif
-	rotator_tb countzero_tb wishbone_bram_tb
+
-
+ifeq ($(USE_DOCKER), 1)
-# XXX
+PWD = $(shell pwd)
-# loadstore_tb fetch_tb
+DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
+GHDL      = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
+CC        = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
+GHDLSYNTH = ghdl
+YOSYS     = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:beta yosys
+NEXTPNR   = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:nextpnr-ecp5 nextpnr-ecp5
+ECPPACK   = $(DOCKERBIN) $(DOCKERARGS) ghdl/synth:trellis ecppack
+OPENOCD   = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb ghdl/synth:prog openocd
+endif
+
+all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
+	rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
 
 all: $(all)
 
-%.o : %.vhdl
+core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
-	$(GHDL) -a $(GHDLFLAGS) --workdir=$(shell dirname $@) $<
+	fetch2.vhdl utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
-
+	decode1.vhdl helpers.vhdl insn_helpers.vhdl gpr_hazard.vhdl \
-common.o: decode_types.o
+	cr_hazard.vhdl control.vhdl decode2.vhdl register_file.vhdl \
-control.o: gpr_hazard.o cr_hazard.o common.o
+	cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
-sim_jtag.o: sim_jtag_socket.o
+	logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
-core_tb.o: common.o wishbone_types.o core.o soc.o sim_jtag.o
+	loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
-core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o loadstore1.o mmu.o dcache.o writeback.o core_debug.o
+	core.vhdl
-core_debug.o: common.o
+
-countzero.o:
+soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl \
-countzero_tb.o: common.o glibc_random.o countzero.o
+	wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl
-cr_file.o: common.o
+
-crhelpers.o: common.o
+soc_sim_files = sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \
-decode1.o: common.o decode_types.o
+	sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl \
-decode2.o: decode_types.o common.o helpers.o insn_helpers.o control.o
+	sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl \
-decode_types.o:
+	sim-unisim/unisim_vcomponents.vhdl dmi_dtm_xilinx.vhdl
-execute1.o: decode_types.o common.o helpers.o crhelpers.o insn_helpers.o ppc_fx_insns.o rotator.o logical.o countzero.o multiply.o divider.o
+
-fetch1.o: common.o
+soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
-fetch2.o: common.o wishbone_types.o
+	sim_jtag_socket_c.c
-glibc_random_helpers.o:
+soc_sim_obj_files=$(soc_sim_c_files:.c=.o)
-glibc_random.o: glibc_random_helpers.o
+comma := ,
-helpers.o:
+soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files))
-cache_ram.o:
+
-plru.o:
+core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
-plru_tb.o: plru.o
+soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
-utils.o:
+
-sim_bram.o: sim_bram_helpers.o utils.o
+$(soc_tbs): %: $(core_files) $(soc_files) $(soc_sim_files) $(soc_sim_obj_files) %.vhdl
-wishbone_bram_wrapper.o: wishbone_types.o sim_bram.o utils.o
+	$(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(core_files) $(soc_files) $(soc_sim_files) $@.vhdl -e $@
-wishbone_bram_tb.o: wishbone_bram_wrapper.o
+
-icache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
+$(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
-icache_tb.o: common.o wishbone_types.o icache.o wishbone_bram_wrapper.o
+	$(GHDL) -c $(GHDLFLAGS) $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
-dcache.o: utils.o common.o wishbone_types.o plru.o cache_ram.o utils.o
+
-dcache_tb.o: common.o wishbone_types.o dcache.o wishbone_bram_wrapper.o
+soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
-insn_helpers.o:
+	$(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
-loadstore1.o: common.o decode_types.o
+
-logical.o: decode_types.o
+# Hello world
-multiply_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o multiply.o
+GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=8192 -gRAM_INIT_FILE=hello_world/hello_world.hex
-multiply.o: common.o decode_types.o
+
-mmu.o: common.o
+# Micropython
-divider_tb.o: decode_types.o common.o glibc_random.o ppc_fx_insns.o divider.o
+#GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=393216 -gRAM_INIT_FILE=micropython/firmware.hex
-divider.o: common.o decode_types.o
+
-ppc_fx_insns.o: helpers.o
+# OrangeCrab with ECP85
-register_file.o: common.o
+GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=50000000 -gCLK_FREQUENCY=50000000
-rotator.o: common.o
+LPF=constraints/orange-crab.lpf
-rotator_tb.o: common.o glibc_random.o ppc_fx_insns.o insn_helpers.o rotator.o
+PACKAGE=CSFBGA285
-sim_console.o:
+NEXTPNR_FLAGS=--um5g-85k --freq 50
-sim_uart.o: wishbone_types.o sim_console.o
+OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
-xics.o: wishbone_types.o common.o
+OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
-soc.o: common.o wishbone_types.o core.o wishbone_arbiter.o sim_uart.o wishbone_bram_wrapper.o dmi_dtm_xilinx.o wishbone_debug_master.o xics.o syscon.o
+
-syscon.o: wishbone_types.o
+# ECP5-EVN
-wishbone_arbiter.o: wishbone_types.o
+#GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=12000000 -gCLK_FREQUENCY=12000000
-wishbone_types.o:
+#LPF=constraints/ecp5-evn.lpf
-writeback.o: common.o crhelpers.o
+#PACKAGE=CABGA381
-dmi_dtm_tb.o: dmi_dtm_xilinx.o wishbone_debug_master.o
+#NEXTPNR_FLAGS=--um5g-85k --freq 12
-dmi_dtm_xilinx.o: wishbone_types.o sim-unisim/unisim_vcomponents.o
+#OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
-wishbone_debug_master.o: wishbone_types.o
+#OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
-
+
-UNISIM_BITS = sim-unisim/unisim_vcomponents.vhdl sim-unisim/BSCANE2.vhdl sim-unisim/BUFG.vhdl
+clkgen=fpga/clk_gen_bypass.vhd
-sim-unisim/unisim_vcomponents.o: $(UNISIM_BITS)
+toplevel=fpga/top-generic.vhdl
-	$(GHDL) -a $(GHDLFLAGS) --work=unisim --workdir=sim-unisim $^
+dmi_dtm=dmi_dtm_dummy.vhdl
-
+
-
+fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
-fpga/soc_reset_tb.o: fpga/soc_reset.o
+	fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl
-
+
-soc_reset_tb: fpga/soc_reset_tb.o fpga/soc_reset.o
+synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
-	$(GHDL) -e $(GHDLFLAGS) --workdir=fpga soc_reset_tb
+
-
+microwatt.json: $(synth_files)
-core_tb: core_tb.o sim_vhpi_c.o sim_bram_helpers_c.o sim_console_c.o sim_jtag_socket_c.o
+	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@"
-	$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o -Wl,sim_console_c.o -Wl,sim_jtag_socket_c.o $@
+
-
+microwatt.v: $(synth_files)
-fetch_tb: fetch_tb.o
+	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
-	$(GHDL) -e $(GHDLFLAGS) $@
+
-
+# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
-icache_tb: icache_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
+microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
-	$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
+	verilator -O3 --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
-
+	make -C obj_dir -f Vmicrowatt.mk
-dcache_tb: dcache_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
+	@cp -f obj_dir/microwatt-verilator microwatt-verilator
-	$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
+
-
+microwatt_out.config: microwatt.json $(LPF)
-plru_tb: plru_tb.o
+	$(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)
-	$(GHDL) -e $(GHDLFLAGS) $@
+
-
+microwatt.bit: microwatt_out.config
-loadstore_tb: loadstore_tb.o
+	$(ECPPACK) --svf microwatt.svf $< $@
-	$(GHDL) -e $(GHDLFLAGS) $@
+
-
+microwatt.svf: microwatt.bit
-multiply_tb: multiply_tb.o
+
-	$(GHDL) -e $(GHDLFLAGS) $@
+prog: microwatt.svf
-
+	$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
-divider_tb: divider_tb.o
-	$(GHDL) -e $(GHDLFLAGS) $@
-
-rotator_tb: rotator_tb.o
-	$(GHDL) -e $(GHDLFLAGS) $@
-
-countzero_tb: countzero_tb.o
-	$(GHDL) -e $(GHDLFLAGS) $@
-
-simple_ram_tb: simple_ram_tb.o
-	$(GHDL) -e $(GHDLFLAGS) $@
-
-wishbone_bram_tb: sim_vhpi_c.o sim_bram_helpers_c.o wishbone_bram_tb.o
-	$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
-
-dmi_dtm_tb: dmi_dtm_tb.o sim_vhpi_c.o sim_bram_helpers_c.o
-	$(GHDL) -e $(GHDLFLAGS) -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o $@
 
 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
@@ -161,6 +161,9 @@ _clean:
 	rm -f TAGS
 	rm -f scripts/mw_debug/*.o
 	rm -f scripts/mw_debug/mw_debug
+	rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
+	rm -f microwatt.v microwatt-verilator
+	rm -rf obj_dir/
 
 clean: _clean
 	make -f scripts/mw_debug/Makefile clean
@@ -174,3 +177,6 @@ distclean: _clean
 	rm -f litedram/gen-src/sdram_init/*~
 	make -f scripts/mw_debug/Makefile distclean
 	make -f hello_world/Makefile distclean
+
+.PHONY: all prog check check_light clean distclean
+.PRECIOUS: microwatt.json microwatt_out.config microwatt.bit

Makefile.synth

@@ -1,88 +0,0 @@
-# Use local tools
-#GHDLSYNTH = ghdl.so
-#YOSYS     = yosys
-#NEXTPNR   = nextpnr-ecp5
-#ECPPACK   = ecppack
-#OPENOCD    = openocd
-
-# Use Docker images
-DOCKER=docker
-#DOCKER=podman
-#
-PWD = $(shell pwd)
-DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
-#
-GHDLSYNTH = ghdl
-YOSYS     = $(DOCKER) $(DOCKERARGS) ghdl/synth:beta yosys
-NEXTPNR   = $(DOCKER) $(DOCKERARGS) ghdl/synth:nextpnr-ecp5 nextpnr-ecp5
-ECPPACK   = $(DOCKER) $(DOCKERARGS) ghdl/synth:trellis ecppack
-OPENOCD   = $(DOCKER) $(DOCKERARGS) --device /dev/bus/usb ghdl/synth:prog openocd
-
-
-# Hello world
-GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=8192 -gRAM_INIT_FILE=hello_world/hello_world.hex
-
-# Micropython
-#GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=393216 -gRAM_INIT_FILE=micropython/firmware.hex
-
-
-# OrangeCrab with ECP85
-#GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=50000000 -gCLK_FREQUENCY=50000000
-#LPF=constraints/orange-crab.lpf
-#PACKAGE=CSFBGA285
-#NEXTPNR_FLAGS=--um5g-85k --freq 50
-#OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
-#OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
-
-# ECP5-EVN
-GHDL_TARGET_GENERICS=-gRESET_LOW=true -gCLK_INPUT=12000000 -gCLK_FREQUENCY=12000000
-LPF=constraints/ecp5-evn.lpf
-PACKAGE=CABGA381
-NEXTPNR_FLAGS=--um5g-85k --freq 12
-OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
-OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
-
-VHDL_FILES  = fpga/soc_reset.vhdl fpga/clk_gen_bypass.vhd decode_types.vhdl
-VHDL_FILES += common.vhdl wishbone_types.vhdl wishbone_debug_master.vhdl
-VHDL_FILES += wishbone_arbiter.vhdl cache_ram.vhdl utils.vhdl plru.vhdl
-VHDL_FILES += helpers.vhdl mmu.vhdl dcache.vhdl core_debug.vhdl fetch1.vhdl fetch2.vhdl
-VHDL_FILES += register_file.vhdl insn_helpers.vhdl multiply.vhdl divider.vhdl
-VHDL_FILES += logical.vhdl crhelpers.vhdl countzero.vhdl rotator.vhdl
-VHDL_FILES += ppc_fx_insns.vhdl execute1.vhdl decode1.vhdl cr_file.vhdl
-VHDL_FILES += writeback.vhdl loadstore1.vhdl icache.vhdl cr_hazard.vhdl
-VHDL_FILES += gpr_hazard.vhdl control.vhdl decode2.vhdl core.vhdl
-VHDL_FILES += fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd dmi_dtm_dummy.vhdl
-VHDL_FILES += fpga/main_bram.vhdl wishbone_bram_wrapper.vhdl syscon.vhdl
-VHDL_FILES += xics.vhdl soc.vhdl fpga/top-generic.vhdl
-
-all: microwatt.bit
-
-microwatt.json: $(VHDL_FILES)
-	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(VHDL_FILES) -e toplevel; synth_ecp5 -json $@"
-
-microwatt.v: $(VHDL_FILES)
-	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(VHDL_FILES) -e toplevel; write_verilog $@"
-
-microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
-	#verilator -O3 -Wall --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
-	verilator -O3 --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
-	make -C obj_dir -f Vmicrowatt.mk
-	@cp -f obj_dir/microwatt-verilator microwatt-verilator
-
-microwatt_out.config: microwatt.json $(LPF)
-	$(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@ $(NEXTPNR_FLAGS) --package $(PACKAGE)
-
-microwatt.bit: microwatt_out.config
-	$(ECPPACK) --svf microwatt.svf $< $@
-
-microwatt.svf: microwatt.bit
-
-prog: microwatt.svf
-	$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
-
-clean:
-	@rm -f work-obj08.cf *.bit *.json *.svf *.config microwatt.v microwatt-verilator
-	@rm -rf obj_dir/
-
-.PHONY: clean prog
-.PRECIOUS: microwatt.json microwatt_out.config microwatt.bit

README.md

@@ -37,7 +37,7 @@ cd ../../../
   appears not to). ghdl with the LLVM backend is likely easier to build.
 
   If building ghdl from scratch is too much for you, the microwatt Makefile
-  supports using Docker or podman images. Read through the Makefile for details.
+  supports using Docker or Podman.
 
 - Next build microwatt:
 
@@ -45,6 +45,17 @@ cd ../../../
 git clone https://github.com/antonblanchard/microwatt
 cd microwatt
 make
+```
+
+   To build using Docker:
+```
+make DOCKER=1
+```
+
+   and to build using Podman:
+
+```
+make PODMAN=1
 ```
 
 - Link in the micropython image:

countzero_tb.vhdl

@@ -109,7 +109,6 @@ begin
             end loop;
         end loop;
 
-        assert false report "end of test" severity failure;
+	std.env.finish;
-        wait;
     end process;
 end behave;

dcache_tb.vhdl

@@ -133,8 +133,6 @@ begin
 	wait until rising_edge(clk);
 	wait until rising_edge(clk);
 
-        assert false report "end of test" severity failure;
+	std.env.finish;
-        wait;
-
     end process;
 end;

divider_tb.vhdl

@@ -547,7 +547,6 @@ begin
             end loop;
         end loop;
 
-        assert false report "end of test" severity failure;
+        std.env.finish;
-        wait;
     end process;
 end behave;

fpga/soc_reset_tb.vhdl

@@ -124,7 +124,6 @@ begin
 
 	wait for clk_period;
 
-        assert false report "end of test" severity failure;
+        std.env.finish;
-        wait;
     end process;
 end behave;

icache_tb.vhdl

@@ -147,8 +147,6 @@ begin
 
         i_out.req <= '0';
 
-        assert false report "end of test" severity failure;
+        std.env.finish;
-        wait;
-
     end process;
 end;

multiply_tb.vhdl

@@ -247,7 +247,7 @@ begin
                 report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
         end loop;
 
-        assert false report "end of test" severity failure;
+        std.env.finish;
         wait;
     end process;
 end behave;

plru_tb.vhdl

@@ -103,7 +103,6 @@ begin
 	wait for clk_period;
 	report "lru:" & to_hstring(lru);
 
-        assert false report "end of test" severity failure;
+        std.env.finish;
-        wait;
     end process;
 end;

rotator_tb.vhdl

@@ -291,7 +291,6 @@ begin
 		report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
         end loop;
 
-        assert false report "end of test" severity failure;
+        std.env.finish;
-        wait;
     end process;
 end behave;

wishbone_bram_tb.vhdl

@@ -169,7 +169,6 @@ begin
         wait until rising_edge(clk);
         assert w_in.ack = '0';
 
-        assert false report "end of test" severity failure;
+        std.env.finish;
-        wait;
     end process;
 end behave;