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@ -1,17 +1,10 @@
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#!/usr/bin/python3
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from fusesoc.capi2.generator import Generator
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from litex.build.tools import write_to_file
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from litex.build.tools import replace_in_file
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.lattice import LatticePlatform
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from litex.soc.integration.builder import *
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from litedram.gen import *
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import subprocess
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import os
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import sys
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import yaml
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import shutil
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def make_new_dir(base, added):
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@ -28,9 +21,6 @@ gen_src_dir = os.path.join(base_dir, "gen-src")
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gen_dir = make_new_dir(base_dir, "generated")
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# Build the init code for microwatt-initialized DRAM
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#
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# XXX Not working yet
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#
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def build_init_code(build_dir, is_sim):
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# More path fudging
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@ -45,7 +35,7 @@ def build_init_code(build_dir, is_sim):
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print(" lx src dir:", lxbios_src_dir)
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# Generate mem.h (hard wire size, it's not important)
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mem_h = "#define MAIN_RAM_BASE 0x40000000\n#define MAIN_RAM_SIZE 0x10000000"
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mem_h = "#define MAIN_RAM_BASE 0x40000000UL\n#define MAIN_RAM_SIZE 0x10000000UL\n"
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write_to_file(os.path.join(gen_inc_dir, "mem.h"), mem_h)
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# Environment
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@ -55,18 +45,19 @@ def build_init_code(build_dir, is_sim):
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def add_var(k, v):
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env_vars.append("{}={}\n".format(k, _makefile_escape(v)))
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add_var("BUILD_DIR", sw_dir)
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add_var("SRC_DIR", src_dir)
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add_var("GENINC_DIR", sw_inc_dir)
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add_var("LXSRC_DIR", lxbios_src_dir)
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makefile = os.path.join(src_dir, "Makefile")
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cmd = ["make", "-C", build_dir, "-f", makefile]
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cmd.append("BUILD_DIR=%s" % sw_dir)
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cmd.append("SRC_DIR=%s" % src_dir)
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cmd.append("GENINC_DIR=%s" % sw_inc_dir)
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cmd.append("LXSRC_DIR=%s" % lxbios_src_dir)
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if is_sim:
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add_var("EXTRA_CFLAGS", "-D__SIM__")
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write_to_file(os.path.join(gen_inc_dir, "variables.mak"), "".join(env_vars))
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cmd.append("EXTRA_CFLAGS=%s" % "-D__SIM__")
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# Build init code
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print(" Generating init software...")
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makefile = os.path.join(src_dir, "Makefile")
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r = subprocess.check_call(["make", "-C", build_dir, "-I", gen_inc_dir, "-f", makefile])
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r = subprocess.check_call(cmd)
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print("Make result:", r)
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return os.path.join(sw_dir, "obj", "sdram_init.hex")
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@ -76,48 +67,17 @@ def generate_one(t):
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print("Generating target:", t)
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# Is it a simulation ?
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is_sim = t is "sim"
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is_sim = "sim" in t
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# Muck with directory path
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build_dir = make_new_dir(build_top_dir, t)
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t_dir = make_new_dir(gen_dir, t)
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# Grab config file
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cfile = os.path.join(gen_src_dir, t + ".yml")
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core_config = yaml.load(open(cfile).read(), Loader=yaml.Loader)
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### TODO: Make most stuff below a function in litedram gen.py and
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### call it rather than duplicate it
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###
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# Convert YAML elements to Python/LiteX
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for k, v in core_config.items():
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replaces = {"False": False, "True": True, "None": None}
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for r in replaces.keys():
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if v == r:
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core_config[k] = replaces[r]
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if "clk_freq" in k:
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core_config[k] = float(core_config[k])
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if k == "sdram_module":
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core_config[k] = getattr(litedram_modules, core_config[k])
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if k == "sdram_phy":
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core_config[k] = getattr(litedram_phys, core_config[k])
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# Generate core
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cmd = ["litedram_gen", "--output-dir=%s" % build_dir]
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if is_sim:
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platform = SimPlatform("", io=[])
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elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis")
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elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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platform = XilinxPlatform("", io=[], toolchain="vivado")
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else:
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raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"]))
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soc = LiteDRAMCore(platform, core_config, is_sim = is_sim, integrated_rom_size=0x6000)
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# Build into build_dir
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builder = Builder(soc, output_dir=build_dir, compile_gateware=False)
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vns = builder.build(build_name="litedram_core", regular_comb=False)
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cmd.append("--sim")
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cmd.append("%s.yml" % t)
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subprocess.check_call(cmd)
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# Grab generated gatewar dir
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gw_dir = os.path.join(build_dir, "gateware")
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