Merge pull request #256 from antonblanchard/flash-reset

Fix a few reset issues in flash controller

spi_flash_ctrl.vhdl

@@ -232,6 +232,10 @@ begin
             if rst = '1' then
                 wb_out.ack   <= '0';
                 wb_out.stall <= '0';
+		wb_stash.cyc <= '0';
+		wb_stash.stb <= '0';
+		wb_stash.sel <= (others => '0');
+		wb_stash.we <= '0';
             else
                 -- Latch wb responses as well for 1 cycle. Stall is updated
                 -- below
@@ -344,12 +348,17 @@ begin
     auto_sync: process(clk)
     begin
         if rising_edge(clk) then
-            auto_state <= auto_next;
+	    if rst = '1' then
-            auto_cnt   <= auto_cnt_next;
+                auto_last_addr <= (others => '0');
-            auto_data  <= auto_data_next;
+		auto_state <= AUTO_BOOT;
-            if auto_latch_adr = '1' then
+	    else
-                auto_last_addr <= auto_lad_next;
+                auto_state <= auto_next;
-            end if;
+                auto_cnt   <= auto_cnt_next;
+                auto_data  <= auto_data_next;
+                if auto_latch_adr = '1' then
+                    auto_last_addr <= auto_lad_next;
+                end if;
+	    end if;
         end if;
     end process;
 
@@ -421,6 +430,8 @@ begin
                     if cmd_ready = '1' then
                         auto_next <= AUTO_IDLE;
                     end if;
+                else
+                    auto_next <= AUTO_IDLE;
                 end if;
             when AUTO_IDLE =>
                 -- Access to the memory map only when manual CS isn't set