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litedram: Use 32-bit CSR bus

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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
jtag-port
Benjamin Herrenschmidt 5 years ago
parent 7f1f6b8525
commit e3013f5754
8 changed files with 2331 additions and 3069 deletions
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2
litedram/gen-src/generate.py
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@ -115,7 +115,7 @@ def generate_one(t, mw_init):
else: else:
raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"])) raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"]))


soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000) soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, csr_data_width=32)


# Build into build_dir # Build into build_dir
builder = Builder(soc, output_dir=build_dir, compile_gateware=False) builder = Builder(soc, output_dir=build_dir, compile_gateware=False)

14
litedram/gen-src/wrapper-mw-init.vhdl
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@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is
user_rst : out std_ulogic; user_rst : out std_ulogic;
csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_adr : in std_ulogic_vector(13 downto 0);
csr_port0_we : in std_ulogic; csr_port0_we : in std_ulogic;
csr_port0_dat_w : in std_ulogic_vector(7 downto 0); csr_port0_dat_w : in std_ulogic_vector(31 downto 0);
csr_port0_dat_r : out std_ulogic_vector(7 downto 0); csr_port0_dat_r : out std_ulogic_vector(31 downto 0);
user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_valid : in std_ulogic;
user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_ready : out std_ulogic;
user_port_native_0_cmd_we : in std_ulogic; user_port_native_0_cmd_we : in std_ulogic;
@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is


signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_adr : std_ulogic_vector(13 downto 0);
signal csr_port0_we : std_ulogic; signal csr_port0_we : std_ulogic;
signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); signal csr_port0_dat_w : std_ulogic_vector(31 downto 0);
signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); signal csr_port0_dat_r : std_ulogic_vector(31 downto 0);
signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0);
signal csr_valid : std_ulogic; signal csr_valid : std_ulogic;
signal csr_write_valid : std_ulogic; signal csr_write_valid : std_ulogic;
@ -205,8 +205,8 @@ begin
-- DRAM CSR interface signals. We only support access to the bottom byte -- DRAM CSR interface signals. We only support access to the bottom byte
csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
csr_write_valid <= wb_in.we and wb_in.sel(0); csr_write_valid <= wb_in.we and wb_in.sel(0);
csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0');
csr_port0_dat_w <= wb_in.dat(7 downto 0); csr_port0_dat_w <= wb_in.dat(31 downto 0);
csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';


-- Wishbone out signals -- Wishbone out signals
@ -215,7 +215,7 @@ begin
user_port0_wdata_ready when state = MWRITE else user_port0_wdata_ready when state = MWRITE else
user_port0_rdata_valid when state = MREAD else '0'; user_port0_rdata_valid when state = MREAD else '0';


csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; csr_port_read_comb <= x"00000000" & csr_port0_dat_r;
wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else
wb_init_out.dat when wb_is_init = '1' else wb_init_out.dat when wb_is_init = '1' else
user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else

14
litedram/generated/arty/litedram-wrapper.vhdl
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@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is
user_rst : out std_ulogic; user_rst : out std_ulogic;
csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_adr : in std_ulogic_vector(13 downto 0);
csr_port0_we : in std_ulogic; csr_port0_we : in std_ulogic;
csr_port0_dat_w : in std_ulogic_vector(7 downto 0); csr_port0_dat_w : in std_ulogic_vector(31 downto 0);
csr_port0_dat_r : out std_ulogic_vector(7 downto 0); csr_port0_dat_r : out std_ulogic_vector(31 downto 0);
user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_valid : in std_ulogic;
user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_ready : out std_ulogic;
user_port_native_0_cmd_we : in std_ulogic; user_port_native_0_cmd_we : in std_ulogic;
@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is


signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_adr : std_ulogic_vector(13 downto 0);
signal csr_port0_we : std_ulogic; signal csr_port0_we : std_ulogic;
signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); signal csr_port0_dat_w : std_ulogic_vector(31 downto 0);
signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); signal csr_port0_dat_r : std_ulogic_vector(31 downto 0);
signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0);
signal csr_valid : std_ulogic; signal csr_valid : std_ulogic;
signal csr_write_valid : std_ulogic; signal csr_write_valid : std_ulogic;
@ -205,8 +205,8 @@ begin
-- DRAM CSR interface signals. We only support access to the bottom byte -- DRAM CSR interface signals. We only support access to the bottom byte
csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
csr_write_valid <= wb_in.we and wb_in.sel(0); csr_write_valid <= wb_in.we and wb_in.sel(0);
csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0');
csr_port0_dat_w <= wb_in.dat(7 downto 0); csr_port0_dat_w <= wb_in.dat(31 downto 0);
csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';


-- Wishbone out signals -- Wishbone out signals
@ -215,7 +215,7 @@ begin
user_port0_wdata_ready when state = MWRITE else user_port0_wdata_ready when state = MWRITE else
user_port0_rdata_valid when state = MREAD else '0'; user_port0_rdata_valid when state = MREAD else '0';


csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; csr_port_read_comb <= x"00000000" & csr_port0_dat_r;
wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else
wb_init_out.dat when wb_is_init = '1' else wb_init_out.dat when wb_is_init = '1' else
user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else

1524
litedram/generated/arty/litedram_core.init
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722
litedram/generated/arty/litedram_core.v
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@ -1,5 +1,5 @@
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:03 // Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:11
//-------------------------------------------------------------------------------- //--------------------------------------------------------------------------------
module litedram_core( module litedram_core(
input wire clk, input wire clk,
@ -24,8 +24,8 @@ module litedram_core(
output wire init_error, output wire init_error,
input wire [13:0] csr_port0_adr, input wire [13:0] csr_port0_adr,
input wire csr_port0_we, input wire csr_port0_we,
input wire [7:0] csr_port0_dat_w, input wire [31:0] csr_port0_dat_w,
output wire [7:0] csr_port0_dat_r, output wire [31:0] csr_port0_dat_r,
output wire user_clk, output wire user_clk,
output wire user_rst, output wire user_rst,
input wire user_port_native_0_cmd_valid, input wire user_port_native_0_cmd_valid,
@ -1485,8 +1485,8 @@ reg init_error_storage = 1'd0;
reg init_error_re = 1'd0; reg init_error_re = 1'd0;
wire [13:0] csr_port_adr; wire [13:0] csr_port_adr;
wire csr_port_we; wire csr_port_we;
wire [7:0] csr_port_dat_w; wire [31:0] csr_port_dat_w;
wire [7:0] csr_port_dat_r; wire [31:0] csr_port_dat_r;
wire user_port_cmd_valid; wire user_port_cmd_valid;
wire user_port_cmd_ready; wire user_port_cmd_ready;
wire user_port_cmd_payload_we; wire user_port_cmd_payload_we;
@ -1566,8 +1566,8 @@ reg new_master_rdata_valid7 = 1'd0;
reg new_master_rdata_valid8 = 1'd0; reg new_master_rdata_valid8 = 1'd0;
wire [13:0] interface0_bank_bus_adr; wire [13:0] interface0_bank_bus_adr;
wire interface0_bank_bus_we; wire interface0_bank_bus_we;
wire [7:0] interface0_bank_bus_dat_w; wire [31:0] interface0_bank_bus_dat_w;
reg [7:0] interface0_bank_bus_dat_r = 8'd0; reg [31:0] interface0_bank_bus_dat_r = 32'd0;
wire csrbank0_init_done0_re; wire csrbank0_init_done0_re;
wire csrbank0_init_done0_r; wire csrbank0_init_done0_r;
wire csrbank0_init_done0_we; wire csrbank0_init_done0_we;
@ -1579,8 +1579,8 @@ wire csrbank0_init_error0_w;
reg csrbank0_sel = 1'd0; reg csrbank0_sel = 1'd0;
wire [13:0] interface1_bank_bus_adr; wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we; wire interface1_bank_bus_we;
wire [7:0] interface1_bank_bus_dat_w; wire [31:0] interface1_bank_bus_dat_w;
reg [7:0] interface1_bank_bus_dat_r = 8'd0; reg [31:0] interface1_bank_bus_dat_r = 32'd0;
wire csrbank1_half_sys8x_taps0_re; wire csrbank1_half_sys8x_taps0_re;
wire [4:0] csrbank1_half_sys8x_taps0_r; wire [4:0] csrbank1_half_sys8x_taps0_r;
wire csrbank1_half_sys8x_taps0_we; wire csrbank1_half_sys8x_taps0_we;
@ -1596,8 +1596,8 @@ wire [1:0] csrbank1_dly_sel0_w;
reg csrbank1_sel = 1'd0; reg csrbank1_sel = 1'd0;
wire [13:0] interface2_bank_bus_adr; wire [13:0] interface2_bank_bus_adr;
wire interface2_bank_bus_we; wire interface2_bank_bus_we;
wire [7:0] interface2_bank_bus_dat_w; wire [31:0] interface2_bank_bus_dat_w;
reg [7:0] interface2_bank_bus_dat_r = 8'd0; reg [31:0] interface2_bank_bus_dat_r = 32'd0;
wire csrbank2_dfii_control0_re; wire csrbank2_dfii_control0_re;
wire [3:0] csrbank2_dfii_control0_r; wire [3:0] csrbank2_dfii_control0_r;
wire csrbank2_dfii_control0_we; wire csrbank2_dfii_control0_we;
@ -1606,199 +1606,87 @@ wire csrbank2_dfii_pi0_command0_re;
wire [5:0] csrbank2_dfii_pi0_command0_r; wire [5:0] csrbank2_dfii_pi0_command0_r;
wire csrbank2_dfii_pi0_command0_we; wire csrbank2_dfii_pi0_command0_we;
wire [5:0] csrbank2_dfii_pi0_command0_w; wire [5:0] csrbank2_dfii_pi0_command0_w;
wire csrbank2_dfii_pi0_address1_re;
wire [5:0] csrbank2_dfii_pi0_address1_r;
wire csrbank2_dfii_pi0_address1_we;
wire [5:0] csrbank2_dfii_pi0_address1_w;
wire csrbank2_dfii_pi0_address0_re; wire csrbank2_dfii_pi0_address0_re;
wire [7:0] csrbank2_dfii_pi0_address0_r; wire [13:0] csrbank2_dfii_pi0_address0_r;
wire csrbank2_dfii_pi0_address0_we; wire csrbank2_dfii_pi0_address0_we;
wire [7:0] csrbank2_dfii_pi0_address0_w; wire [13:0] csrbank2_dfii_pi0_address0_w;
wire csrbank2_dfii_pi0_baddress0_re; wire csrbank2_dfii_pi0_baddress0_re;
wire [2:0] csrbank2_dfii_pi0_baddress0_r; wire [2:0] csrbank2_dfii_pi0_baddress0_r;
wire csrbank2_dfii_pi0_baddress0_we; wire csrbank2_dfii_pi0_baddress0_we;
wire [2:0] csrbank2_dfii_pi0_baddress0_w; wire [2:0] csrbank2_dfii_pi0_baddress0_w;
wire csrbank2_dfii_pi0_wrdata3_re;
wire [7:0] csrbank2_dfii_pi0_wrdata3_r;
wire csrbank2_dfii_pi0_wrdata3_we;
wire [7:0] csrbank2_dfii_pi0_wrdata3_w;
wire csrbank2_dfii_pi0_wrdata2_re;
wire [7:0] csrbank2_dfii_pi0_wrdata2_r;
wire csrbank2_dfii_pi0_wrdata2_we;
wire [7:0] csrbank2_dfii_pi0_wrdata2_w;
wire csrbank2_dfii_pi0_wrdata1_re;
wire [7:0] csrbank2_dfii_pi0_wrdata1_r;
wire csrbank2_dfii_pi0_wrdata1_we;
wire [7:0] csrbank2_dfii_pi0_wrdata1_w;
wire csrbank2_dfii_pi0_wrdata0_re; wire csrbank2_dfii_pi0_wrdata0_re;
wire [7:0] csrbank2_dfii_pi0_wrdata0_r; wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
wire csrbank2_dfii_pi0_wrdata0_we; wire csrbank2_dfii_pi0_wrdata0_we;
wire [7:0] csrbank2_dfii_pi0_wrdata0_w; wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
wire csrbank2_dfii_pi0_rddata3_re; wire csrbank2_dfii_pi0_rddata_re;
wire [7:0] csrbank2_dfii_pi0_rddata3_r; wire [31:0] csrbank2_dfii_pi0_rddata_r;
wire csrbank2_dfii_pi0_rddata3_we; wire csrbank2_dfii_pi0_rddata_we;
wire [7:0] csrbank2_dfii_pi0_rddata3_w; wire [31:0] csrbank2_dfii_pi0_rddata_w;
wire csrbank2_dfii_pi0_rddata2_re;
wire [7:0] csrbank2_dfii_pi0_rddata2_r;
wire csrbank2_dfii_pi0_rddata2_we;
wire [7:0] csrbank2_dfii_pi0_rddata2_w;
wire csrbank2_dfii_pi0_rddata1_re;
wire [7:0] csrbank2_dfii_pi0_rddata1_r;
wire csrbank2_dfii_pi0_rddata1_we;
wire [7:0] csrbank2_dfii_pi0_rddata1_w;
wire csrbank2_dfii_pi0_rddata0_re;
wire [7:0] csrbank2_dfii_pi0_rddata0_r;
wire csrbank2_dfii_pi0_rddata0_we;
wire [7:0] csrbank2_dfii_pi0_rddata0_w;
wire csrbank2_dfii_pi1_command0_re; wire csrbank2_dfii_pi1_command0_re;
wire [5:0] csrbank2_dfii_pi1_command0_r; wire [5:0] csrbank2_dfii_pi1_command0_r;
wire csrbank2_dfii_pi1_command0_we; wire csrbank2_dfii_pi1_command0_we;
wire [5:0] csrbank2_dfii_pi1_command0_w; wire [5:0] csrbank2_dfii_pi1_command0_w;
wire csrbank2_dfii_pi1_address1_re;
wire [5:0] csrbank2_dfii_pi1_address1_r;
wire csrbank2_dfii_pi1_address1_we;
wire [5:0] csrbank2_dfii_pi1_address1_w;
wire csrbank2_dfii_pi1_address0_re; wire csrbank2_dfii_pi1_address0_re;
wire [7:0] csrbank2_dfii_pi1_address0_r; wire [13:0] csrbank2_dfii_pi1_address0_r;
wire csrbank2_dfii_pi1_address0_we; wire csrbank2_dfii_pi1_address0_we;
wire [7:0] csrbank2_dfii_pi1_address0_w; wire [13:0] csrbank2_dfii_pi1_address0_w;
wire csrbank2_dfii_pi1_baddress0_re; wire csrbank2_dfii_pi1_baddress0_re;
wire [2:0] csrbank2_dfii_pi1_baddress0_r; wire [2:0] csrbank2_dfii_pi1_baddress0_r;
wire csrbank2_dfii_pi1_baddress0_we; wire csrbank2_dfii_pi1_baddress0_we;
wire [2:0] csrbank2_dfii_pi1_baddress0_w; wire [2:0] csrbank2_dfii_pi1_baddress0_w;
wire csrbank2_dfii_pi1_wrdata3_re;
wire [7:0] csrbank2_dfii_pi1_wrdata3_r;
wire csrbank2_dfii_pi1_wrdata3_we;
wire [7:0] csrbank2_dfii_pi1_wrdata3_w;
wire csrbank2_dfii_pi1_wrdata2_re;
wire [7:0] csrbank2_dfii_pi1_wrdata2_r;
wire csrbank2_dfii_pi1_wrdata2_we;
wire [7:0] csrbank2_dfii_pi1_wrdata2_w;
wire csrbank2_dfii_pi1_wrdata1_re;
wire [7:0] csrbank2_dfii_pi1_wrdata1_r;
wire csrbank2_dfii_pi1_wrdata1_we;
wire [7:0] csrbank2_dfii_pi1_wrdata1_w;
wire csrbank2_dfii_pi1_wrdata0_re; wire csrbank2_dfii_pi1_wrdata0_re;
wire [7:0] csrbank2_dfii_pi1_wrdata0_r; wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
wire csrbank2_dfii_pi1_wrdata0_we; wire csrbank2_dfii_pi1_wrdata0_we;
wire [7:0] csrbank2_dfii_pi1_wrdata0_w; wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
wire csrbank2_dfii_pi1_rddata3_re; wire csrbank2_dfii_pi1_rddata_re;
wire [7:0] csrbank2_dfii_pi1_rddata3_r; wire [31:0] csrbank2_dfii_pi1_rddata_r;
wire csrbank2_dfii_pi1_rddata3_we; wire csrbank2_dfii_pi1_rddata_we;
wire [7:0] csrbank2_dfii_pi1_rddata3_w; wire [31:0] csrbank2_dfii_pi1_rddata_w;
wire csrbank2_dfii_pi1_rddata2_re;
wire [7:0] csrbank2_dfii_pi1_rddata2_r;
wire csrbank2_dfii_pi1_rddata2_we;
wire [7:0] csrbank2_dfii_pi1_rddata2_w;
wire csrbank2_dfii_pi1_rddata1_re;
wire [7:0] csrbank2_dfii_pi1_rddata1_r;
wire csrbank2_dfii_pi1_rddata1_we;
wire [7:0] csrbank2_dfii_pi1_rddata1_w;
wire csrbank2_dfii_pi1_rddata0_re;
wire [7:0] csrbank2_dfii_pi1_rddata0_r;
wire csrbank2_dfii_pi1_rddata0_we;
wire [7:0] csrbank2_dfii_pi1_rddata0_w;
wire csrbank2_dfii_pi2_command0_re; wire csrbank2_dfii_pi2_command0_re;
wire [5:0] csrbank2_dfii_pi2_command0_r; wire [5:0] csrbank2_dfii_pi2_command0_r;
wire csrbank2_dfii_pi2_command0_we; wire csrbank2_dfii_pi2_command0_we;
wire [5:0] csrbank2_dfii_pi2_command0_w; wire [5:0] csrbank2_dfii_pi2_command0_w;
wire csrbank2_dfii_pi2_address1_re;
wire [5:0] csrbank2_dfii_pi2_address1_r;
wire csrbank2_dfii_pi2_address1_we;
wire [5:0] csrbank2_dfii_pi2_address1_w;
wire csrbank2_dfii_pi2_address0_re; wire csrbank2_dfii_pi2_address0_re;
wire [7:0] csrbank2_dfii_pi2_address0_r; wire [13:0] csrbank2_dfii_pi2_address0_r;
wire csrbank2_dfii_pi2_address0_we; wire csrbank2_dfii_pi2_address0_we;
wire [7:0] csrbank2_dfii_pi2_address0_w; wire [13:0] csrbank2_dfii_pi2_address0_w;
wire csrbank2_dfii_pi2_baddress0_re; wire csrbank2_dfii_pi2_baddress0_re;
wire [2:0] csrbank2_dfii_pi2_baddress0_r; wire [2:0] csrbank2_dfii_pi2_baddress0_r;
wire csrbank2_dfii_pi2_baddress0_we; wire csrbank2_dfii_pi2_baddress0_we;
wire [2:0] csrbank2_dfii_pi2_baddress0_w; wire [2:0] csrbank2_dfii_pi2_baddress0_w;
wire csrbank2_dfii_pi2_wrdata3_re;
wire [7:0] csrbank2_dfii_pi2_wrdata3_r;
wire csrbank2_dfii_pi2_wrdata3_we;
wire [7:0] csrbank2_dfii_pi2_wrdata3_w;
wire csrbank2_dfii_pi2_wrdata2_re;
wire [7:0] csrbank2_dfii_pi2_wrdata2_r;
wire csrbank2_dfii_pi2_wrdata2_we;
wire [7:0] csrbank2_dfii_pi2_wrdata2_w;
wire csrbank2_dfii_pi2_wrdata1_re;
wire [7:0] csrbank2_dfii_pi2_wrdata1_r;
wire csrbank2_dfii_pi2_wrdata1_we;
wire [7:0] csrbank2_dfii_pi2_wrdata1_w;
wire csrbank2_dfii_pi2_wrdata0_re; wire csrbank2_dfii_pi2_wrdata0_re;
wire [7:0] csrbank2_dfii_pi2_wrdata0_r; wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
wire csrbank2_dfii_pi2_wrdata0_we; wire csrbank2_dfii_pi2_wrdata0_we;
wire [7:0] csrbank2_dfii_pi2_wrdata0_w; wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
wire csrbank2_dfii_pi2_rddata3_re; wire csrbank2_dfii_pi2_rddata_re;
wire [7:0] csrbank2_dfii_pi2_rddata3_r; wire [31:0] csrbank2_dfii_pi2_rddata_r;
wire csrbank2_dfii_pi2_rddata3_we; wire csrbank2_dfii_pi2_rddata_we;
wire [7:0] csrbank2_dfii_pi2_rddata3_w; wire [31:0] csrbank2_dfii_pi2_rddata_w;
wire csrbank2_dfii_pi2_rddata2_re;
wire [7:0] csrbank2_dfii_pi2_rddata2_r;
wire csrbank2_dfii_pi2_rddata2_we;
wire [7:0] csrbank2_dfii_pi2_rddata2_w;
wire csrbank2_dfii_pi2_rddata1_re;
wire [7:0] csrbank2_dfii_pi2_rddata1_r;
wire csrbank2_dfii_pi2_rddata1_we;
wire [7:0] csrbank2_dfii_pi2_rddata1_w;
wire csrbank2_dfii_pi2_rddata0_re;
wire [7:0] csrbank2_dfii_pi2_rddata0_r;
wire csrbank2_dfii_pi2_rddata0_we;
wire [7:0] csrbank2_dfii_pi2_rddata0_w;
wire csrbank2_dfii_pi3_command0_re; wire csrbank2_dfii_pi3_command0_re;
wire [5:0] csrbank2_dfii_pi3_command0_r; wire [5:0] csrbank2_dfii_pi3_command0_r;
wire csrbank2_dfii_pi3_command0_we; wire csrbank2_dfii_pi3_command0_we;
wire [5:0] csrbank2_dfii_pi3_command0_w; wire [5:0] csrbank2_dfii_pi3_command0_w;
wire csrbank2_dfii_pi3_address1_re;
wire [5:0] csrbank2_dfii_pi3_address1_r;
wire csrbank2_dfii_pi3_address1_we;
wire [5:0] csrbank2_dfii_pi3_address1_w;
wire csrbank2_dfii_pi3_address0_re; wire csrbank2_dfii_pi3_address0_re;
wire [7:0] csrbank2_dfii_pi3_address0_r; wire [13:0] csrbank2_dfii_pi3_address0_r;
wire csrbank2_dfii_pi3_address0_we; wire csrbank2_dfii_pi3_address0_we;
wire [7:0] csrbank2_dfii_pi3_address0_w; wire [13:0] csrbank2_dfii_pi3_address0_w;
wire csrbank2_dfii_pi3_baddress0_re; wire csrbank2_dfii_pi3_baddress0_re;
wire [2:0] csrbank2_dfii_pi3_baddress0_r; wire [2:0] csrbank2_dfii_pi3_baddress0_r;
wire csrbank2_dfii_pi3_baddress0_we; wire csrbank2_dfii_pi3_baddress0_we;
wire [2:0] csrbank2_dfii_pi3_baddress0_w; wire [2:0] csrbank2_dfii_pi3_baddress0_w;
wire csrbank2_dfii_pi3_wrdata3_re;
wire [7:0] csrbank2_dfii_pi3_wrdata3_r;
wire csrbank2_dfii_pi3_wrdata3_we;
wire [7:0] csrbank2_dfii_pi3_wrdata3_w;
wire csrbank2_dfii_pi3_wrdata2_re;
wire [7:0] csrbank2_dfii_pi3_wrdata2_r;
wire csrbank2_dfii_pi3_wrdata2_we;
wire [7:0] csrbank2_dfii_pi3_wrdata2_w;
wire csrbank2_dfii_pi3_wrdata1_re;
wire [7:0] csrbank2_dfii_pi3_wrdata1_r;
wire csrbank2_dfii_pi3_wrdata1_we;
wire [7:0] csrbank2_dfii_pi3_wrdata1_w;
wire csrbank2_dfii_pi3_wrdata0_re; wire csrbank2_dfii_pi3_wrdata0_re;
wire [7:0] csrbank2_dfii_pi3_wrdata0_r; wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
wire csrbank2_dfii_pi3_wrdata0_we; wire csrbank2_dfii_pi3_wrdata0_we;
wire [7:0] csrbank2_dfii_pi3_wrdata0_w; wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
wire csrbank2_dfii_pi3_rddata3_re; wire csrbank2_dfii_pi3_rddata_re;
wire [7:0] csrbank2_dfii_pi3_rddata3_r; wire [31:0] csrbank2_dfii_pi3_rddata_r;
wire csrbank2_dfii_pi3_rddata3_we; wire csrbank2_dfii_pi3_rddata_we;
wire [7:0] csrbank2_dfii_pi3_rddata3_w; wire [31:0] csrbank2_dfii_pi3_rddata_w;
wire csrbank2_dfii_pi3_rddata2_re;
wire [7:0] csrbank2_dfii_pi3_rddata2_r;
wire csrbank2_dfii_pi3_rddata2_we;
wire [7:0] csrbank2_dfii_pi3_rddata2_w;
wire csrbank2_dfii_pi3_rddata1_re;
wire [7:0] csrbank2_dfii_pi3_rddata1_r;
wire csrbank2_dfii_pi3_rddata1_we;
wire [7:0] csrbank2_dfii_pi3_rddata1_w;
wire csrbank2_dfii_pi3_rddata0_re;
wire [7:0] csrbank2_dfii_pi3_rddata0_r;
wire csrbank2_dfii_pi3_rddata0_we;
wire [7:0] csrbank2_dfii_pi3_rddata0_w;
reg csrbank2_sel = 1'd0; reg csrbank2_sel = 1'd0;
wire [13:0] adr; wire [13:0] adr;
wire we; wire we;
wire [7:0] dat_w; wire [31:0] dat_w;
wire [7:0] dat_r; wire [31:0] dat_r;
reg rhs_array_muxed0 = 1'd0; reg rhs_array_muxed0 = 1'd0;
reg [13:0] rhs_array_muxed1 = 14'd0; reg [13:0] rhs_array_muxed1 = 14'd0;
reg [2:0] rhs_array_muxed2 = 3'd0; reg [2:0] rhs_array_muxed2 = 3'd0;
@ -10730,7 +10618,7 @@ reg dummy_d_282;
// synthesis translate_on // synthesis translate_on
always @(*) begin always @(*) begin
csrbank0_sel <= 1'd0; csrbank0_sel <= 1'd0;
csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2); csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2);
if (interface0_bank_bus_adr[0]) begin if (interface0_bank_bus_adr[0]) begin
csrbank0_sel <= 1'd0; csrbank0_sel <= 1'd0;
end end
@ -10739,11 +10627,11 @@ always @(*) begin
// synthesis translate_on // synthesis translate_on
end end
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0)); assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0));
assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0)); assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0));
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1)); assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1));
assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1)); assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1));
assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage; assign csrbank0_init_error0_w = init_error_storage;


@ -10752,7 +10640,7 @@ reg dummy_d_283;
// synthesis translate_on // synthesis translate_on
always @(*) begin always @(*) begin
csrbank1_sel <= 1'd0; csrbank1_sel <= 1'd0;
csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0); csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0);
if (interface1_bank_bus_adr[0]) begin if (interface1_bank_bus_adr[0]) begin
csrbank1_sel <= 1'd0; csrbank1_sel <= 1'd0;
end end
@ -10761,35 +10649,35 @@ always @(*) begin
// synthesis translate_on // synthesis translate_on
end end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0)); assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0));
assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0)); assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0));
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1)); assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1));
assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1)); assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1));
assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2)); assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2));
assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2)); assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2));
assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3)); assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3));
assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3)); assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3));
assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4)); assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4));
assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4)); assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4));
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5)); assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5));
assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5)); assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5));
assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6)); assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6));
assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6)); assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6));
assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7)); assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7));
assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7)); assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7));
assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8));
assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8));
assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9)); assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9));
assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9)); assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9));
assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
@ -10799,7 +10687,7 @@ reg dummy_d_284;
// synthesis translate_on // synthesis translate_on
always @(*) begin always @(*) begin
csrbank2_sel <= 1'd0; csrbank2_sel <= 1'd0;
csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1); csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1);
if (interface2_bank_bus_adr[0]) begin if (interface2_bank_bus_adr[0]) begin
csrbank2_sel <= 1'd0; csrbank2_sel <= 1'd0;
end end
@ -10808,217 +10696,105 @@ always @(*) begin
// synthesis translate_on // synthesis translate_on
end end
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0)); assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0));
assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0)); assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0));
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1)); assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1));
assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1)); assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1));
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2)); assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2));
assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2)); assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2));
assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[5:0]; assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0];
assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3)); assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3));
assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3)); assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3));
assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4));
assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4));
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5)); assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4));
assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5)); assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4));
assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0]; assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6)); assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5));
assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6)); assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5));
assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0]; assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7)); assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6));
assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7)); assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6));
assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8));
assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8));
assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9));
assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9));
assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10));
assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10));
assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11));
assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11));
assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12));
assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12));
assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13));
assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13));
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14)); assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7));
assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14)); assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7));
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15)); assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8));
assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15)); assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8));
assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[5:0]; assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0];
assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16)); assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9));
assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16)); assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9));
assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17));
assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17));
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18)); assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10));
assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18)); assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10));
assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0]; assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19)); assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11));
assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19)); assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11));
assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0]; assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20)); assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12));
assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20)); assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12));
assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21));
assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21));
assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22));
assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22));
assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23));
assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23));
assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24));
assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24));
assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25));
assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25));
assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26));
assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26));
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27)); assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13));
assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27)); assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13));
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28)); assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14));
assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28)); assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14));
assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[5:0]; assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0];
assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29)); assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15));
assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29)); assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15));
assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30));
assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30));
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31)); assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16));
assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31)); assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16));
assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0]; assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32)); assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17));
assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32)); assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17));
assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0]; assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33)); assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18));
assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33)); assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18));
assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34));
assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34));
assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35));
assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35));
assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36));
assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36));
assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37));
assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37));
assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38));
assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38));
assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39));
assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39));
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40)); assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19));
assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40)); assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19));
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41)); assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20));
assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41)); assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20));
assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[5:0]; assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0];
assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42)); assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21));
assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42)); assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21));
assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43));
assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43));
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44)); assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22));
assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44)); assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22));
assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0]; assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45)); assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23));
assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45)); assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23));
assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0]; assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46)); assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24));
assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46)); assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24));
assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47));
assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47));
assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48));
assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48));
assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49));
assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49));
assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50));
assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50));
assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51));
assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51));
assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0];
assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52));
assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52));
assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8]; assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0];
assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24]; assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16]; assign csrbank2_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8]; assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata_we;
assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0];
assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24];
assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16];
assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8];
assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0];
assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we;
assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8]; assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0];
assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24]; assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16]; assign csrbank2_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8]; assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata_we;
assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0];
assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24];
assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16];
assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8];
assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0];
assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we;
assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8]; assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0];
assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24]; assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16]; assign csrbank2_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8]; assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata_we;
assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0];
assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24];
assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16];
assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8];
assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0];
assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we;
assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8]; assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0];
assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24]; assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16]; assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8]; assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we;
assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0];
assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24];
assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16];
assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8];
assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0];
assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we;
assign adr = csr_port_adr; assign adr = csr_port_adr;
assign we = csr_port_we; assign we = csr_port_we;
assign dat_w = csr_port_dat_w; assign dat_w = csr_port_dat_w;
@ -14159,7 +13935,7 @@ always @(posedge sys_clk) begin
new_master_rdata_valid8 <= new_master_rdata_valid7; new_master_rdata_valid8 <= new_master_rdata_valid7;
interface0_bank_bus_dat_r <= 1'd0; interface0_bank_bus_dat_r <= 1'd0;
if (csrbank0_sel) begin if (csrbank0_sel) begin
case (interface0_bank_bus_adr[3]) case (interface0_bank_bus_adr[1])
1'd0: begin 1'd0: begin
interface0_bank_bus_dat_r <= csrbank0_init_done0_w; interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
end end
@ -14178,7 +13954,7 @@ always @(posedge sys_clk) begin
init_error_re <= csrbank0_init_error0_re; init_error_re <= csrbank0_init_error0_re;
interface1_bank_bus_dat_r <= 1'd0; interface1_bank_bus_dat_r <= 1'd0;
if (csrbank1_sel) begin if (csrbank1_sel) begin
case (interface1_bank_bus_adr[6:3]) case (interface1_bank_bus_adr[4:1])
1'd0: begin 1'd0: begin
interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
end end
@ -14225,7 +14001,7 @@ always @(posedge sys_clk) begin
a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
interface2_bank_bus_dat_r <= 1'd0; interface2_bank_bus_dat_r <= 1'd0;
if (csrbank2_sel) begin if (csrbank2_sel) begin
case (interface2_bank_bus_adr[8:3]) case (interface2_bank_bus_adr[5:1])
1'd0: begin 1'd0: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
end end
@ -14236,154 +14012,70 @@ always @(posedge sys_clk) begin
interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
end end
2'd3: begin 2'd3: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
end end
3'd4: begin 3'd4: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
end end
3'd5: begin 3'd5: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
end end
3'd6: begin 3'd6: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
end end
3'd7: begin 3'd7: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
end end
4'd8: begin 4'd8: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
end end
4'd9: begin 4'd9: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
end end
4'd10: begin 4'd10: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
end end
4'd11: begin 4'd11: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
end end
4'd12: begin 4'd12: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
end end
4'd13: begin 4'd13: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
end end
4'd14: begin 4'd14: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
end end
4'd15: begin 4'd15: begin
interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
end end
5'd16: begin 5'd16: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
end end
5'd17: begin 5'd17: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
end end
5'd18: begin 5'd18: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
end end
5'd19: begin 5'd19: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w;
end
5'd20: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w;
end
5'd21: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
end
5'd22: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
end
5'd23: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w;
end
5'd24: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w;
end
5'd25: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
end
5'd26: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
end
5'd27: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
end
5'd28: begin
interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
end
5'd29: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w;
end
5'd30: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
end
5'd31: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
end
6'd32: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w;
end
6'd33: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w;
end
6'd34: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w;
end
6'd35: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
end
6'd36: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w;
end
6'd37: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w;
end
6'd38: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w;
end
6'd39: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w;
end
6'd40: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
end end
6'd41: begin 5'd20: begin
interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
end end
6'd42: begin 5'd21: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w;
end
6'd43: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
end end
6'd44: begin 5'd22: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
end end
6'd45: begin 5'd23: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w;
end
6'd46: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w;
end
6'd47: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w;
end
6'd48: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
end end
6'd49: begin 5'd24: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w; interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
end
6'd50: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w;
end
6'd51: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w;
end
6'd52: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w;
end end
endcase endcase
end end
@ -14395,112 +14087,64 @@ always @(posedge sys_clk) begin
litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
end end
litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
if (csrbank2_dfii_pi0_address1_re) begin
litedramcore_phaseinjector0_address_storage[13:8] <= csrbank2_dfii_pi0_address1_r;
end
if (csrbank2_dfii_pi0_address0_re) begin if (csrbank2_dfii_pi0_address0_re) begin
litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r; litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
end end
litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
if (csrbank2_dfii_pi0_baddress0_re) begin if (csrbank2_dfii_pi0_baddress0_re) begin
litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
end end
litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
if (csrbank2_dfii_pi0_wrdata3_re) begin
litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r;
end
if (csrbank2_dfii_pi0_wrdata2_re) begin
litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r;
end
if (csrbank2_dfii_pi0_wrdata1_re) begin
litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r;
end
if (csrbank2_dfii_pi0_wrdata0_re) begin if (csrbank2_dfii_pi0_wrdata0_re) begin
litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r; litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
end end
litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
if (csrbank2_dfii_pi1_command0_re) begin if (csrbank2_dfii_pi1_command0_re) begin
litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
end end
litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
if (csrbank2_dfii_pi1_address1_re) begin
litedramcore_phaseinjector1_address_storage[13:8] <= csrbank2_dfii_pi1_address1_r;
end
if (csrbank2_dfii_pi1_address0_re) begin if (csrbank2_dfii_pi1_address0_re) begin
litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r; litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
end end
litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
if (csrbank2_dfii_pi1_baddress0_re) begin if (csrbank2_dfii_pi1_baddress0_re) begin
litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
end end
litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
if (csrbank2_dfii_pi1_wrdata3_re) begin
litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r;
end
if (csrbank2_dfii_pi1_wrdata2_re) begin
litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r;
end
if (csrbank2_dfii_pi1_wrdata1_re) begin
litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r;
end
if (csrbank2_dfii_pi1_wrdata0_re) begin if (csrbank2_dfii_pi1_wrdata0_re) begin
litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r; litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
end end
litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
if (csrbank2_dfii_pi2_command0_re) begin if (csrbank2_dfii_pi2_command0_re) begin
litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
end end
litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
if (csrbank2_dfii_pi2_address1_re) begin
litedramcore_phaseinjector2_address_storage[13:8] <= csrbank2_dfii_pi2_address1_r;
end
if (csrbank2_dfii_pi2_address0_re) begin if (csrbank2_dfii_pi2_address0_re) begin
litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r; litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
end end
litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
if (csrbank2_dfii_pi2_baddress0_re) begin if (csrbank2_dfii_pi2_baddress0_re) begin
litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
end end
litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
if (csrbank2_dfii_pi2_wrdata3_re) begin
litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r;
end
if (csrbank2_dfii_pi2_wrdata2_re) begin
litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r;
end
if (csrbank2_dfii_pi2_wrdata1_re) begin
litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r;
end
if (csrbank2_dfii_pi2_wrdata0_re) begin if (csrbank2_dfii_pi2_wrdata0_re) begin
litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r; litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
end end
litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
if (csrbank2_dfii_pi3_command0_re) begin if (csrbank2_dfii_pi3_command0_re) begin
litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
end end
litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
if (csrbank2_dfii_pi3_address1_re) begin
litedramcore_phaseinjector3_address_storage[13:8] <= csrbank2_dfii_pi3_address1_r;
end
if (csrbank2_dfii_pi3_address0_re) begin if (csrbank2_dfii_pi3_address0_re) begin
litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r; litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
end end
litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
if (csrbank2_dfii_pi3_baddress0_re) begin if (csrbank2_dfii_pi3_baddress0_re) begin
litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
end end
litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
if (csrbank2_dfii_pi3_wrdata3_re) begin
litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r;
end
if (csrbank2_dfii_pi3_wrdata2_re) begin
litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r;
end
if (csrbank2_dfii_pi3_wrdata1_re) begin
litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r;
end
if (csrbank2_dfii_pi3_wrdata0_re) begin if (csrbank2_dfii_pi3_wrdata0_re) begin
litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r; litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
end end
litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
if (sys_rst) begin if (sys_rst) begin

14
litedram/generated/nexys-video/litedram-wrapper.vhdl
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@ -82,8 +82,8 @@ architecture behaviour of litedram_wrapper is
user_rst : out std_ulogic; user_rst : out std_ulogic;
csr_port0_adr : in std_ulogic_vector(13 downto 0); csr_port0_adr : in std_ulogic_vector(13 downto 0);
csr_port0_we : in std_ulogic; csr_port0_we : in std_ulogic;
csr_port0_dat_w : in std_ulogic_vector(7 downto 0); csr_port0_dat_w : in std_ulogic_vector(31 downto 0);
csr_port0_dat_r : out std_ulogic_vector(7 downto 0); csr_port0_dat_r : out std_ulogic_vector(31 downto 0);
user_port_native_0_cmd_valid : in std_ulogic; user_port_native_0_cmd_valid : in std_ulogic;
user_port_native_0_cmd_ready : out std_ulogic; user_port_native_0_cmd_ready : out std_ulogic;
user_port_native_0_cmd_we : in std_ulogic; user_port_native_0_cmd_we : in std_ulogic;
@ -116,8 +116,8 @@ architecture behaviour of litedram_wrapper is


signal csr_port0_adr : std_ulogic_vector(13 downto 0); signal csr_port0_adr : std_ulogic_vector(13 downto 0);
signal csr_port0_we : std_ulogic; signal csr_port0_we : std_ulogic;
signal csr_port0_dat_w : std_ulogic_vector(7 downto 0); signal csr_port0_dat_w : std_ulogic_vector(31 downto 0);
signal csr_port0_dat_r : std_ulogic_vector(7 downto 0); signal csr_port0_dat_r : std_ulogic_vector(31 downto 0);
signal csr_port_read_comb : std_ulogic_vector(63 downto 0); signal csr_port_read_comb : std_ulogic_vector(63 downto 0);
signal csr_valid : std_ulogic; signal csr_valid : std_ulogic;
signal csr_write_valid : std_ulogic; signal csr_write_valid : std_ulogic;
@ -205,8 +205,8 @@ begin
-- DRAM CSR interface signals. We only support access to the bottom byte -- DRAM CSR interface signals. We only support access to the bottom byte
csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr; csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
csr_write_valid <= wb_in.we and wb_in.sel(0); csr_write_valid <= wb_in.we and wb_in.sel(0);
csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0'); csr_port0_adr <= wb_in.adr(15 downto 2) when wb_is_csr = '1' else (others => '0');
csr_port0_dat_w <= wb_in.dat(7 downto 0); csr_port0_dat_w <= wb_in.dat(31 downto 0);
csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0'; csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';


-- Wishbone out signals -- Wishbone out signals
@ -215,7 +215,7 @@ begin
user_port0_wdata_ready when state = MWRITE else user_port0_wdata_ready when state = MWRITE else
user_port0_rdata_valid when state = MREAD else '0'; user_port0_rdata_valid when state = MREAD else '0';


csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r; csr_port_read_comb <= x"00000000" & csr_port0_dat_r;
wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else
wb_init_out.dat when wb_is_init = '1' else wb_init_out.dat when wb_is_init = '1' else
user_port0_rdata_data(127 downto 64) when ad3 = '1' else user_port0_rdata_data(127 downto 64) when ad3 = '1' else

1422
litedram/generated/nexys-video/litedram_core.init
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1688
litedram/generated/nexys-video/litedram_core.v
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