matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Merge pull request #79 from deece/uart_address

Browse Source 
Tighten UART address
jtag-port
Anton Blanchard 5 years ago committed by GitHub
parent 3c6e66dc96 ccd52bf6f2
commit e54db5b496
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File

8
soc.vhdl
Unescape Escape View File

@ -106,7 +106,7 @@ begin
-- Wishbone slaves address decoder & mux -- Wishbone slaves address decoder & mux
slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out) slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
-- Selected slave -- Selected slave
type slave_type is (SLAVE_UART, type slave_type is (SLAVE_UART_0,
SLAVE_MEMORY, SLAVE_MEMORY,
SLAVE_NONE); SLAVE_NONE);
variable slave : slave_type; variable slave : slave_type;
@ -116,8 +116,8 @@ begin
if wb_master_out.adr(63 downto 24) = x"0000000000" then if wb_master_out.adr(63 downto 24) = x"0000000000" then
slave := SLAVE_MEMORY; slave := SLAVE_MEMORY;
elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then
if wb_master_out.adr(15 downto 12) = x"2" then if wb_master_out.adr(23 downto 12) = x"002" then
slave := SLAVE_UART; slave := SLAVE_UART_0;
end if; end if;
end if; end if;


@ -130,7 +130,7 @@ begin
when SLAVE_MEMORY => when SLAVE_MEMORY =>
wb_bram_in.cyc <= wb_master_out.cyc; wb_bram_in.cyc <= wb_master_out.cyc;
wb_master_in <= wb_bram_out; wb_master_in <= wb_bram_out;
when SLAVE_UART => when SLAVE_UART_0 =>
wb_uart0_in.cyc <= wb_master_out.cyc; wb_uart0_in.cyc <= wb_master_out.cyc;
wb_master_in <= wb_uart0_out; wb_master_in <= wb_uart0_out;
when others => when others =>

Write Preview
Loading…
Cancel
Save