divider: Always compute result/sresult/d_out.write_reg_data

These are intended to be combinatorial.  The previous code was giving
warnings in vivado about registers/latches with no clock defined.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

divider.vhdl

@@ -108,9 +108,6 @@ begin
         d_out <= DividerToWritebackInit;
         d_out.write_reg_nr <= write_reg;
 
-        if count(6) = '1' then
-            d_out.valid <= '1';
-            d_out.write_reg_enable <= '1';
         if is_modulus = '1' then
             result <= dend(127 downto 64);
         else
@@ -122,6 +119,10 @@ begin
             sresult <= result;
         end if;
         d_out.write_reg_data <= sresult;
+
+        if count(6) = '1' then
+            d_out.valid <= '1';
+            d_out.write_reg_enable <= '1';
             if rc = '1' then
                 d_out.write_cr_enable <= '1';
                 d_out.write_cr_mask <= num_to_fxm(0);