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@ -22,7 +22,6 @@ architecture behaviour of divider is
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signal result : std_ulogic_vector(63 downto 0);
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signal result : std_ulogic_vector(63 downto 0);
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signal sresult : std_ulogic_vector(64 downto 0);
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signal sresult : std_ulogic_vector(64 downto 0);
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signal oresult : std_ulogic_vector(63 downto 0);
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signal oresult : std_ulogic_vector(63 downto 0);
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signal qbit : std_ulogic;
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signal running : std_ulogic;
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signal running : std_ulogic;
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signal signcheck : std_ulogic;
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signal signcheck : std_ulogic;
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signal count : unsigned(6 downto 0);
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signal count : unsigned(6 downto 0);
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