Reduce simulated and default FPGA RAM to 384kB

Micropython has been able to fit into 384kB for ages, so lets reduce our
simulated RAM. This is useful for testing if micropython will run on an
ECP5 85k, which has enough BRAM for 384kB but not enough for 512kB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

core_tb.vhdl

@@ -19,7 +19,7 @@ begin
     soc0: entity work.soc
 	generic map(
 	    SIM => true,
-	    MEMORY_SIZE => 524288,
+	    MEMORY_SIZE => (384*1024),
 	    RAM_INIT_FILE => "main_ram.bin",
 	    RESET_LOW => false
 	    )

fpga/toplevel.vhdl

@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
 
 entity toplevel is
     generic (
-	MEMORY_SIZE   : positive := 524288;
+	MEMORY_SIZE   : positive := (384*1024);
 	RAM_INIT_FILE : string   := "firmware.hex";
 	RESET_LOW     : boolean  := true;
 	CLK_INPUT     : positive := 100000000;