forked from cores/microwatt
loadstore: Convert to 3-stage pipeline
This makes loadstore use a 3-stage pipeline. For now, only one instruction goes through the pipe at a time. Completion and writeback are still combinatorial off the valid signal back from the dcache, so performance should be the same as before. In future it should be able to sustain one load or store per cycle provided they hit in the dcache. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>cache-tlb-parameters-2
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f636bb7c39
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f583d088b7