uart: Make 16550 the default

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
jtag-port
Benjamin Herrenschmidt 4 years ago
parent b230677e93
commit fb5c16d05e

@ -24,7 +24,7 @@ entity toplevel is
LOG_LENGTH : natural := 512; LOG_LENGTH : natural := 512;
USE_LITEETH : boolean := false; USE_LITEETH : boolean := false;
UART_IS_16550 : boolean := false; UART_IS_16550 : boolean := false;
HAS_UART1 : boolean := false HAS_UART1 : boolean := true
); );
port( port(
ext_clk : in std_ulogic; ext_clk : in std_ulogic;

@ -12,7 +12,7 @@ entity toplevel is
CLK_INPUT : positive := 100000000; CLK_INPUT : positive := 100000000;
CLK_FREQUENCY : positive := 100000000; CLK_FREQUENCY : positive := 100000000;
DISABLE_FLATTEN_CORE : boolean := false; DISABLE_FLATTEN_CORE : boolean := false;
UART_IS_16550 : boolean := false UART_IS_16550 : boolean := true
); );
port( port(
ext_clk : in std_ulogic; ext_clk : in std_ulogic;

@ -20,7 +20,7 @@ entity toplevel is
SPI_FLASH_OFFSET : integer := 10485760; SPI_FLASH_OFFSET : integer := 10485760;
SPI_FLASH_DEF_CKDV : natural := 1; SPI_FLASH_DEF_CKDV : natural := 1;
SPI_FLASH_DEF_QUAD : boolean := true; SPI_FLASH_DEF_QUAD : boolean := true;
UART_IS_16550 : boolean := false; UART_IS_16550 : boolean := true;
); );
port( port(
ext_clk : in std_ulogic; ext_clk : in std_ulogic;

@ -315,7 +315,7 @@ parameters:
datatype : bool datatype : bool
description : Use 16550-compatible UART from OpenCores description : Use 16550-compatible UART from OpenCores
paramtype : generic paramtype : generic
default : false default : true


has_uart1: has_uart1:
datatype : bool datatype : bool

@ -63,7 +63,7 @@ entity soc is
SPI_FLASH_DEF_QUAD : boolean := false; SPI_FLASH_DEF_QUAD : boolean := false;
LOG_LENGTH : natural := 512; LOG_LENGTH : natural := 512;
HAS_LITEETH : boolean := false; HAS_LITEETH : boolean := false;
UART0_IS_16550 : boolean := false; UART0_IS_16550 : boolean := true;
HAS_UART1 : boolean := false HAS_UART1 : boolean := false
); );
port( port(

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