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@ -73,6 +73,11 @@ filesets:
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- fpga/arty_a7-35.xdc : {file_type : xdc}
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- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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arty_a7-100:
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files:
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- fpga/arty_a7-35.xdc : {file_type : xdc}
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- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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cmod_a7-35:
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files:
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- fpga/cmod_a7-35.xdc : {file_type : xdc}
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@ -103,6 +108,14 @@ targets:
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vivado: {part : xc7a35ticsg324-1L}
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toplevel : toplevel
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arty_a7-100:
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default_tool: vivado
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filesets: [core, arty_a7-100, soc, fpga, debug_xilinx]
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parameters : [memory_size, ram_init_file]
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tools:
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vivado: {part : xc7a100ticsg324-1L}
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toplevel : toplevel
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cmod_a7-35:
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default_tool: vivado
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filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
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