Merge pull request #75 from paulusmack/master

fpga: Add definitions for Arty A7-100 board
jtag-port
Anton Blanchard 5 years ago committed by GitHub
commit feb8ee7149
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@ -73,6 +73,11 @@ filesets:
- fpga/arty_a7-35.xdc : {file_type : xdc} - fpga/arty_a7-35.xdc : {file_type : xdc}
- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}


arty_a7-100:
files:
- fpga/arty_a7-35.xdc : {file_type : xdc}
- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}

cmod_a7-35: cmod_a7-35:
files: files:
- fpga/cmod_a7-35.xdc : {file_type : xdc} - fpga/cmod_a7-35.xdc : {file_type : xdc}
@ -103,6 +108,14 @@ targets:
vivado: {part : xc7a35ticsg324-1L} vivado: {part : xc7a35ticsg324-1L}
toplevel : toplevel toplevel : toplevel


arty_a7-100:
default_tool: vivado
filesets: [core, arty_a7-100, soc, fpga, debug_xilinx]
parameters : [memory_size, ram_init_file]
tools:
vivado: {part : xc7a100ticsg324-1L}
toplevel : toplevel

cmod_a7-35: cmod_a7-35:
default_tool: vivado default_tool: vivado
filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx] filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]

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