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@ -26,6 +26,7 @@ use work.wishbone_types.all;
@@ -26,6 +26,7 @@ use work.wishbone_types.all;
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-- 0xc0006000: SPI Flash controller |
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-- 0xc0007000: GPIO controller |
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-- 0xc8nnnnnn: External IO bus |
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-- 0xcb000000: LPC slave (same addr as Kestral) |
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-- 0xf0000000: Flash "ROM" mapping |
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-- 0xff000000: DRAM init code (if any) or flash ROM (**) |
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@ -50,6 +51,8 @@ use work.wishbone_types.all;
@@ -50,6 +51,8 @@ use work.wishbone_types.all;
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-- 2 : UART1 |
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-- 3 : SD card |
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-- 4 : GPIO |
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-- 5 : LPC UART |
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-- 6 : LPC IPMI |
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entity soc is |
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generic ( |
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@ -60,6 +63,7 @@ entity soc is
@@ -60,6 +63,7 @@ entity soc is
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HAS_FPU : boolean := true; |
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HAS_BTC : boolean := true; |
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HAS_SHORT_MULT : boolean := false; |
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HAS_LPC : boolean := false; |
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DISABLE_FLATTEN_CORE : boolean := false; |
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HAS_DRAM : boolean := false; |
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DRAM_SIZE : integer := 0; |
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@ -129,6 +133,17 @@ entity soc is
@@ -129,6 +133,17 @@ entity soc is
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gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0); |
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gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0'); |
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-- LPC signals |
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lpc_data_o : out std_ulogic_vector(3 downto 0); |
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lpc_data_oe : out std_ulogic; |
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lpc_data_i : in std_ulogic_vector(3 downto 0) := (others => '1'); |
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lpc_frame_n : in std_ulogic := '1'; |
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lpc_reset_n : in std_ulogic := '1'; |
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lpc_clock : in std_ulogic := '1'; |
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lpc_irq_o : out std_ulogic; |
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lpc_irq_oe : out std_ulogic; |
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lpc_irq_i : in std_ulogic := '0'; |
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-- DRAM controller signals |
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alt_reset : in std_ulogic := '0' |
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); |
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@ -146,7 +161,7 @@ architecture behaviour of soc is
@@ -146,7 +161,7 @@ architecture behaviour of soc is
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-- Arbiter array (ghdl doesnt' support assigning the array |
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-- elements in the entity instantiation) |
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constant NUM_WB_MASTERS : positive := 4; |
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constant NUM_WB_MASTERS : positive := 5; |
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signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1); |
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signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1); |
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@ -187,6 +202,26 @@ architecture behaviour of soc is
@@ -187,6 +202,26 @@ architecture behaviour of soc is
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signal wb_spiflash_is_reg : std_ulogic; |
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signal wb_spiflash_is_map : std_ulogic; |
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-- LPC Flash controller signals: |
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signal wb_lpc_in : wb_io_master_out; |
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signal wb_lpc_out : wb_io_slave_out; |
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signal lpc_vuart_irq : std_ulogic; |
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signal lpc_ipmi_irq : std_ulogic; |
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-- LPC master wb |
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signal lpc_master_wb_cyc : std_ulogic; |
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signal lpc_master_wb_stb : std_ulogic; |
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signal lpc_master_wb_err : std_ulogic; |
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signal lpc_master_wb_addr : std_ulogic_vector(29 downto 0); |
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signal wb_lpc_dma_out : wb_io_master_out := wb_io_master_out_init; |
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signal wb_lpc_dma_in : wb_io_slave_out; |
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signal wb_lpc_dma_nr : wb_io_master_out; |
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signal wb_lpc_dma_ir : wb_io_slave_out; |
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-- for conversion from non-pipelined wishbone to pipelined |
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signal wb_lpc_dma_stb_sent : std_ulogic; |
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-- XICS signals: |
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signal wb_xics_icp_in : wb_io_master_out; |
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signal wb_xics_icp_out : wb_io_slave_out; |
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@ -225,6 +260,7 @@ architecture behaviour of soc is
@@ -225,6 +260,7 @@ architecture behaviour of soc is
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signal rst_core : std_ulogic := '1'; |
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signal rst_uart : std_ulogic := '1'; |
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signal rst_xics : std_ulogic := '1'; |
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signal rst_lpc : std_ulogic := '1'; |
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signal rst_spi : std_ulogic := '1'; |
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signal rst_gpio : std_ulogic := '1'; |
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signal rst_bram : std_ulogic := '1'; |
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@ -243,6 +279,7 @@ architecture behaviour of soc is
@@ -243,6 +279,7 @@ architecture behaviour of soc is
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SLAVE_IO_SPI_FLASH_MAP, |
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SLAVE_IO_GPIO, |
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SLAVE_IO_EXTERNAL, |
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SLAVE_IO_LPC, |
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SLAVE_IO_NONE); |
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signal slave_io_dbg : slave_io_type; |
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@ -312,6 +349,7 @@ begin
@@ -312,6 +349,7 @@ begin
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rst_spi <= rst; |
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rst_xics <= rst; |
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rst_gpio <= rst; |
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rst_lpc <= rst; |
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rst_bram <= rst; |
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rst_dtm <= rst; |
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rst_wbar <= rst; |
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@ -360,11 +398,13 @@ begin
@@ -360,11 +398,13 @@ begin
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wb_masters_out <= (0 => wishbone_dcore_out, |
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1 => wishbone_icore_out, |
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2 => wishbone_widen_data(wishbone_dma_out), |
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3 => wishbone_debug_out); |
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3 => wishbone_widen_data(wb_lpc_dma_out), |
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4 => wishbone_debug_out); |
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wishbone_dcore_in <= wb_masters_in(0); |
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wishbone_icore_in <= wb_masters_in(1); |
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wishbone_dma_in <= wishbone_narrow_data(wb_masters_in(2), wishbone_dma_out.adr); |
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wishbone_debug_in <= wb_masters_in(3); |
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wb_lpc_dma_in <= wishbone_narrow_data(wb_masters_in(3), wb_lpc_dma_out.adr); |
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wishbone_debug_in <= wb_masters_in(4); |
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wishbone_arbiter_0: entity work.wishbone_arbiter |
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generic map( |
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NUM_MASTERS => NUM_WB_MASTERS |
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@ -616,6 +656,8 @@ begin
@@ -616,6 +656,8 @@ begin
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slave_io := SLAVE_IO_UART1; |
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elsif std_match(match, x"C8---") then |
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slave_io := SLAVE_IO_EXTERNAL; |
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elsif std_match(match, x"CB---") then |
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slave_io := SLAVE_IO_LPC; |
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elsif std_match(match, x"C0004") then |
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slave_io := SLAVE_IO_ICP; |
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elsif std_match(match, x"C0005") then |
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@ -636,6 +678,8 @@ begin
@@ -636,6 +678,8 @@ begin
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wb_spiflash_is_map <= '0'; |
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wb_gpio_in <= wb_sio_out; |
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wb_gpio_in.cyc <= '0'; |
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wb_lpc_in <= wb_sio_out; |
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wb_lpc_in.cyc <= '0'; |
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-- Only give xics 8 bits of wb addr (for now...) |
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wb_xics_icp_in <= wb_sio_out; |
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@ -693,6 +737,9 @@ begin
@@ -693,6 +737,9 @@ begin
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wb_sio_in <= wb_ext_io_out; |
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end if; |
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when SLAVE_IO_LPC => |
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wb_lpc_in.cyc <= wb_sio_out.cyc; |
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wb_sio_in <= wb_lpc_out; |
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when SLAVE_IO_SYSCON => |
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wb_syscon_in.cyc <= wb_sio_out.cyc; |
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wb_sio_in <= wb_syscon_out; |
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@ -892,6 +939,115 @@ begin
@@ -892,6 +939,115 @@ begin
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wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack; |
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end generate; |
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lpc_gen: if HAS_LPC generate |
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component lpc_top port ( |
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clk : in std_ulogic; |
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rst : in std_ulogic; |
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lclk : in std_ulogic; |
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lframe : in std_ulogic; |
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lreset : in std_ulogic; |
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lad_en : out std_ulogic; |
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lad_out : out std_ulogic_vector(3 downto 0); |
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lad_in : in std_ulogic_vector(3 downto 0); |
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adr : in std_ulogic_vector(13 downto 0); |
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dat_w : in std_ulogic_vector(31 downto 0); |
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dat_r : out std_ulogic_vector(31 downto 0); |
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ack : out std_ulogic; |
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cyc : in std_ulogic; |
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sel : in std_ulogic; |
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stb : in std_ulogic; |
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we : in std_ulogic; |
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dma_adr : out std_ulogic_vector(29 downto 0); |
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dma_dat_w : out std_ulogic_vector(31 downto 0); |
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dma_dat_r : in std_ulogic_vector(31 downto 0); |
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dma_ack : in std_ulogic; |
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dma_cyc : out std_ulogic; |
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dma_sel : out std_ulogic_vector(3 downto 0); |
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dma_stb : out std_ulogic; |
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dma_we : out std_ulogic; |
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bmc_ipmi_irq : out std_ulogic; |
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bmc_vuart_irq : out std_ulogic; |
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target_ipmi_irq : out std_ulogic; |
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target_vuart_irq : out std_ulogic |
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); |
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end component; |
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begin |
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lpc0: lpc_top |
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port map( |
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rst => rst_lpc, |
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clk => system_clk, |
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adr => wb_lpc_in.adr(13 downto 0), |
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dat_w => wb_lpc_in.dat(31 downto 0), |
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dat_r => wb_lpc_out.dat(31 downto 0), |
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ack => wb_lpc_out.ack, |
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cyc => wb_lpc_in.cyc, |
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sel => wb_lpc_in.sel(0), |
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stb => wb_lpc_in.stb, |
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we => wb_lpc_in.we, |
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dma_adr => wb_lpc_dma_nr.adr(29 downto 0), |
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dma_dat_w => wb_lpc_dma_nr.dat(31 downto 0), |
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dma_dat_r => wb_lpc_dma_ir.dat(31 downto 0), |
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dma_sel => wb_lpc_dma_nr.sel, |
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dma_cyc => wb_lpc_dma_nr.cyc, |
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dma_stb => wb_lpc_dma_nr.stb, |
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dma_ack => wb_lpc_dma_ir.ack, |
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dma_we => wb_lpc_dma_nr.we, |
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lclk => lpc_clock, |
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lframe => lpc_frame_n, |
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lreset => lpc_reset_n, |
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lad_out => lpc_data_o, |
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lad_in => lpc_data_i, |
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lad_en => lpc_data_oe, |
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bmc_ipmi_irq => lpc_ipmi_irq, |
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bmc_vuart_irq => lpc_vuart_irq |
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); |
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lpc_master_wb_err <= '0'; |
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lpc_irq_o <= '0'; |
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lpc_irq_oe <= '0'; |
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-- FIXME hook up irqs |
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wb_lpc_out.stall <= not wb_lpc_out.ack; |
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-- Convert non-pipelined DMA wishbone to pipelined by suppressing |
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-- non-acknowledged strobes |
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process(system_clk) |
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begin |
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if rising_edge(system_clk) then |
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wb_lpc_dma_out <= wb_lpc_dma_nr; |
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if wb_lpc_dma_stb_sent = '1' or |
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(wb_lpc_dma_out.stb = '1' and wb_lpc_dma_in.stall = '0') then |
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wb_lpc_dma_out.stb <= '0'; |
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end if; |
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if wb_lpc_dma_nr.cyc = '0' or wb_lpc_dma_ir.ack = '1' then |
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wb_lpc_dma_stb_sent <= '0'; |
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elsif wb_lpc_dma_in.stall = '0' then |
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wb_lpc_dma_stb_sent <= wb_lpc_dma_nr.stb; |
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end if; |
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wb_lpc_dma_ir <= wb_lpc_dma_in; |
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end if; |
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end process; |
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end generate; |
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no_lpc_gen: if not HAS_LPC generate |
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lpc_data_o <= (others => '0'); |
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lpc_data_oe <= '0'; |
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lpc_irq_o <= '0'; |
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lpc_irq_oe <= '0'; |
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wb_lpc_out.dat <= (others => '1'); |
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wb_lpc_out.ack <= wb_lpc_in.cyc and wb_lpc_in.stb; |
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wb_lpc_out.stall <= wb_lpc_in.cyc and not wb_lpc_out.ack; |
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end generate; |
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xics_icp: entity work.xics_icp |
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port map( |
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clk => system_clk, |
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@ -942,6 +1098,8 @@ begin
@@ -942,6 +1098,8 @@ begin
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int_level_in(2) <= uart1_irq; |
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int_level_in(3) <= ext_irq_sdcard; |
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int_level_in(4) <= gpio_intr; |
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int_level_in(5) <= lpc_vuart_irq; |
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int_level_in(6) <= lpc_ipmi_irq; |
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end process; |
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-- BRAM Memory slave |
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