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Author SHA1 Message Date
Anton Blanchard 986881f258 Add a patch to route the NIA out to GPIOs 5 years ago

@ -22,6 +22,7 @@ entity core is


-- Added for debug, ghdl doesn't support external names unfortunately -- Added for debug, ghdl doesn't support external names unfortunately
registers : out regfile; registers : out regfile;
nia_out : out std_ulogic_vector(61 downto 0);
terminate_out : out std_ulogic terminate_out : out std_ulogic
); );
end core; end core;
@ -149,7 +150,8 @@ begin
r_in => register_file_to_decode2, r_in => register_file_to_decode2,
r_out => decode2_to_register_file, r_out => decode2_to_register_file,
c_in => cr_file_to_decode2, c_in => cr_file_to_decode2,
c_out => decode2_to_cr_file c_out => decode2_to_cr_file,
nia_out => nia_out
); );


register_file_0: entity work.register_file register_file_0: entity work.register_file

@ -28,7 +28,9 @@ entity decode2 is
r_out : out Decode2ToRegisterFileType; r_out : out Decode2ToRegisterFileType;


c_in : in CrFileToDecode2Type; c_in : in CrFileToDecode2Type;
c_out : out Decode2ToCrFileType c_out : out Decode2ToCrFileType;

nia_out : out std_ulogic_vector(63 downto 2)
); );
end entity decode2; end entity decode2;


@ -188,7 +190,9 @@ begin
decode2_0: process(clk) decode2_0: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
nia_out <= (others => '0');
if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' then if rin.e.valid = '1' or rin.l.valid = '1' or rin.m.valid = '1' then
nia_out <= rin.e.nia(63 downto 2);
report "execute " & to_hstring(rin.e.nia); report "execute " & to_hstring(rin.e.nia);
end if; end if;
r <= rin; r <= rin;

@ -6,5 +6,24 @@ set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports ext_rst]
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports uart0_txd] set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports uart0_txd]
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart0_rxd] set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart0_rxd]


set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L10N_T1_D15_14 Sch=ja[1]
set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L10P_T1_D14_14 Sch=ja[2]
set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L8N_T1_D12_14 Sch=ja[8]
set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja[9]
set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]

set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L21P_T3_DQS_34 Sch=jb_p[1]
set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L21N_T3_DQS_34 Sch=jb_n[1]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L19P_T3_34 Sch=jb_p[2]
set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L19N_T3_VREF_34 Sch=jb_n[2]
set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L24P_T3_34 Sch=jb_p[3]
set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L24N_T3_34 Sch=jb_n[3]
set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L23P_T3_34 Sch=jb_p[4]
set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L23N_T3_34 Sch=jb_n[4]

set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]


@ -13,7 +13,11 @@ entity toplevel is


-- UART0 signals: -- UART0 signals:
uart0_txd : out std_ulogic; uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic uart0_rxd : in std_ulogic;

-- NIA out on GPIOs
ja : out std_ulogic_vector(7 downto 0);
jb : out std_ulogic_vector(7 downto 0)
); );
end entity toplevel; end entity toplevel;


@ -27,7 +31,10 @@ architecture behaviour of toplevel is
signal system_clk : std_ulogic; signal system_clk : std_ulogic;
signal system_clk_locked : std_ulogic; signal system_clk_locked : std_ulogic;


signal nia : std_ulogic_vector(61 downto 0);
begin begin
ja <= nia(7 downto 0);
jb <= nia(15 downto 8);


reset_controller: entity work.soc_reset reset_controller: entity work.soc_reset
generic map( generic map(
@ -62,7 +69,8 @@ begin
system_clk => system_clk, system_clk => system_clk,
rst => soc_rst, rst => soc_rst,
uart0_txd => uart0_txd, uart0_txd => uart0_txd,
uart0_rxd => uart0_rxd uart0_rxd => uart0_rxd,
nia_out => nia
); );


end architecture behaviour; end architecture behaviour;

@ -24,7 +24,9 @@ entity soc is


-- UART0 signals: -- UART0 signals:
uart0_txd : out std_ulogic; uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic uart0_rxd : in std_ulogic;

nia_out : out std_ulogic_vector(61 downto 0)
); );
end entity soc; end entity soc;


@ -69,7 +71,8 @@ begin
wishbone_data_in => wishbone_dcore_in, wishbone_data_in => wishbone_dcore_in,
wishbone_data_out => wishbone_dcore_out, wishbone_data_out => wishbone_dcore_out,
registers => registers, registers => registers,
terminate_out => terminate terminate_out => terminate,
nia_out => nia_out
); );


-- Wishbone bus master arbiter & mux -- Wishbone bus master arbiter & mux

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