Use a record for cache parameters

The number of generics we pass down from the top level is getting a
bit unwieldy. Paul suggests using records to group them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

.github/workflows/test.yml

@@ -5,19 +5,12 @@ on:
   pull_request:
   schedule:
     - cron: '0 0 * * 5'
-  workflow_dispatch:
 
 jobs:
 
   build:
     runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        backend:
-        - llvm
-        - gcc
-    container: ghdl/vunit:${{ matrix.backend }}
+    container: ghdl/vunit:llvm
     steps:
     - uses: actions/checkout@v2
     - run: make GNATMAKE='gnatmake -j'$(nproc)
@@ -40,6 +33,7 @@ jobs:
       max-parallel: 3
       matrix:
         task: [
+          "tests_unit",
           "tests_console",
           "{1..99}",
           "{100..199}",
@@ -58,24 +52,16 @@ jobs:
     - uses: actions/checkout@v2
     - run: bash -c "make -j$(nproc) ${{ matrix.task }}"
 
-  VUnit:
-    needs: [build]
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v2
-    - uses: docker://ghdl/vunit:llvm
-      with:
-        args: python3 ./run.py -p10
-
   symbiflow:
     strategy:
       fail-fast: false
       max-parallel: 2
       matrix:
-        task: [ ECP5-EVN, ORANGE-CRAB, ORANGE-CRAB-0.21 ]
+        task: [ ECP5-EVN, ORANGE-CRAB ]
     runs-on: ubuntu-latest
     env:
       DOCKER: 1
+      SYNTH_ECP5_FLAGS: -noflatten
       FPGA_TARGET: ${{matrix.task}}
     steps:
     - uses: actions/checkout@v2
@@ -93,17 +79,3 @@ jobs:
     steps:
     - uses: actions/checkout@v2
     - run: make DOCKER=1 microwatt.v
-
-  verilator:
-    runs-on: ubuntu-latest
-    env:
-      DOCKER: 1
-      FPGA_TARGET: verilator
-      RAM_INIT_FILE: micropython/firmware.hex
-      MEMORY_SIZE: 524288
-    steps:
-    - uses: actions/checkout@v2
-    - run: |
-        sudo apt update
-        sudo apt install -y python3-pexpect
-        make -j$(nproc) test_micropython_verilator test_micropython_verilator_long

.gitignore

@@ -13,5 +13,4 @@ tests/*/*.hex
 tests/*/*.elf
 TAGS
 litedram/build/*
-liteeth/build/*
 obj_dir/*

Makefile

@@ -1,22 +1,12 @@
 GHDL ?= ghdl
-GHDLFLAGS=--std=08
+GHDLFLAGS=--std=08 -frelaxed
 CFLAGS=-O3 -Wall
-# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
-VERILATOR_FLAGS=-O3 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
-# It takes forever to build with optimisation, so disable by default
-#VERILATOR_CFLAGS=-O3
 
-# some yosys builds have ghdl plugin built in, otherwise need "-m ghdl"
-GHDLSYNTH ?= $(shell ($(YOSYS) -H | grep -q ghdl) || echo -m ghdl)
+GHDLSYNTH ?= ghdl.so
 YOSYS     ?= yosys
 NEXTPNR   ?= nextpnr-ecp5
 ECPPACK   ?= ecppack
-ECPPROG   ?= ecpprog
 OPENOCD   ?= openocd
-VUNITRUN  ?= python3 ./run.py
-VERILATOR ?= verilator
-DFUUTIL   ?= dfu-util
-DFUSUFFIX ?= dfu-suffix
 
 # We need a version of GHDL built with either the LLVM or gcc backend.
 # Fedora provides this, but other distros may not. Another option is to use
@@ -39,41 +29,37 @@ PWD = $(shell pwd)
 DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
 GHDL      = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
 CC        = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
-GHDLSYNTH = -m ghdl
+GHDLSYNTH = ghdl
 YOSYS     = $(DOCKERBIN) $(DOCKERARGS) hdlc/ghdl:yosys yosys
 NEXTPNR   = $(DOCKERBIN) $(DOCKERARGS) hdlc/nextpnr:ecp5 nextpnr-ecp5
 ECPPACK   = $(DOCKERBIN) $(DOCKERARGS) hdlc/prjtrellis ecppack
 OPENOCD   = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb hdlc/prog openocd
-VUNITRUN  = $(DOCKERBIN) $(DOCKERARGS) ghdl/vunit:llvm python3 ./run.py
-VERILATOR = $(DOCKERBIN) $(DOCKERARGS) verilator/verilator:latest
 endif
 
-VUNITARGS += -p10
-
-all = core_tb icache_tb dcache_tb dmi_dtm_tb \
-	wishbone_bram_tb soc_reset_tb
+all = core_tb icache_tb dcache_tb multiply_tb dmi_dtm_tb divider_tb \
+	rotator_tb countzero_tb wishbone_bram_tb soc_reset_tb
 
 all: $(all)
 
-core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
+core_files = params.vhdl decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
 	utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \
 	decode1.vhdl helpers.vhdl insn_helpers.vhdl \
 	control.vhdl decode2.vhdl register_file.vhdl \
 	cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
-	logical.vhdl countbits.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
+	logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \
 	loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
-	core.vhdl fpu.vhdl pmu.vhdl
+	core.vhdl fpu.vhdl
 
-soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
-	wishbone_debug_master.vhdl xics.vhdl syscon.vhdl gpio.vhdl soc.vhdl \
+soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
+	wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
 	spi_rxtx.vhdl spi_flash_ctrl.vhdl
 
 uart_files = $(wildcard uart16550/*.v)
 
-soc_sim_files = $(core_files) $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
+soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
 	sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
 	sim_16550_uart.vhdl \
-	foreign_random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl
+	random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl
 
 soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
 	sim_jtag_socket_c.c
@@ -90,6 +76,7 @@ $(unisim_lib): $(unisim_lib_files)
 	$(GHDL) -i --std=08 --work=unisim --workdir=$(unisim_dir) $^
 GHDLFLAGS += -P$(unisim_dir)
 
+core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
 soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
 soc_flash_tbs = core_flash_tb
 soc_dram_tbs = dram_tb core_dram_tb
@@ -115,6 +102,9 @@ $(soc_flash_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) $(fmf_l
 $(soc_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) %.vhdl
 	$(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $@.vhdl -e $@
 
+$(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl
+	$(GHDL) -c $(GHDLFLAGS) $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl $@.vhdl -e $@
+
 soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
 	$(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
 
@@ -125,8 +115,10 @@ $(soc_dram_tbs):
 	$(error "Verilator is required to make this target !")
 else
 
+VERILATOR_CFLAGS=-O3
+VERILATOR_FLAGS=-O3
 verilated_dram: litedram/generated/sim/litedram_core.v
-	verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $<
+	verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace
 	make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
 
 SIM_DRAM_CFLAGS  = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
@@ -134,7 +126,7 @@ SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -fa
 sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
 	$(CC)  $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
 
-soc_dram_files = $(core_files) $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
+soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
 soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
 soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
 dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
@@ -145,54 +137,25 @@ $(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_f
 endif
 
 # Hello world
-MEMORY_SIZE ?=8192
-RAM_INIT_FILE ?=hello_world/hello_world.hex
+MEMORY_SIZE=8192
+RAM_INIT_FILE=hello_world/hello_world.hex
 
 # Micropython
 #MEMORY_SIZE=393216
 #RAM_INIT_FILE=micropython/firmware.hex
 
-FPGA_TARGET ?= ORANGE-CRAB-0.21
-
-# FIXME: icache RAMs aren't being inferrenced as block RAMs on ECP5
-# with yosys, so make it smaller for now as a workaround.
-ICACHE_NUM_LINES=4
-
-clkgen=fpga/clk_gen_ecp5.vhd
-toplevel=fpga/top-generic.vhdl
-dmi_dtm=dmi_dtm_dummy.vhdl
-LITEDRAM_GHDL_ARG=
+FPGA_TARGET ?= ORANGE-CRAB
 
-# OrangeCrab with ECP85 (original v0.0 with UM5G-85 chip)
+# OrangeCrab with ECP85
 ifeq ($(FPGA_TARGET), ORANGE-CRAB)
 RESET_LOW=true
-CLK_INPUT=48000000
-CLK_FREQUENCY=48000000
+CLK_INPUT=50000000
+CLK_FREQUENCY=40000000
 LPF=constraints/orange-crab.lpf
 PACKAGE=CSFBGA285
-NEXTPNR_FLAGS=--um5g-85k --freq 48
+NEXTPNR_FLAGS=--um5g-85k --freq 40
 OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
-ECP_FLASH_OFFSET=0x80000
-endif
-
-# OrangeCrab with ECP85 (v0.21)
-ifeq ($(FPGA_TARGET), ORANGE-CRAB-0.21)
-RESET_LOW=true
-CLK_INPUT=48000000
-CLK_FREQUENCY=48000000
-LPF=constraints/orange-crab-0.2.lpf
-PACKAGE=CSFBGA285
-NEXTPNR_FLAGS=--85k --speed 8 --freq 48 --timing-allow-fail --ignore-loops
-OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
-OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg
-DFU_VENDOR=1209
-DFU_PRODUCT=5af0
-ECP_FLASH_OFFSET=0x80000
-toplevel=fpga/top-orangecrab0.2.vhdl
-litedram_target=orangecrab-85-0.2
-soc_extra_v += litesdcard/generated/lattice/litesdcard_core.v
-dmi_dtm=dmi_dtm_ecp5.vhdl
 endif
 
 # ECP5-EVN
@@ -207,17 +170,12 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 endif
 
-ifneq ($(litedram_target),)
-soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \
-	litedram/generated/$(litedram_target)/litedram-initmem.vhdl
-soc_extra_v += litedram/generated/$(litedram_target)/litedram_core.v
-LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=true
-endif
-
 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
-	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) \
-	$(LITEDRAM_GHDL_ARG)
+	-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY)
 
+clkgen=fpga/clk_gen_ecp5.vhd
+toplevel=fpga/top-generic.vhdl
+dmi_dtm=dmi_dtm_dummy.vhdl
 
 ifeq ($(FPGA_TARGET), verilator)
 RESET_LOW=true
@@ -226,20 +184,22 @@ CLK_FREQUENCY=50000000
 clkgen=fpga/clk_gen_bypass.vhd
 endif
 
-fpga_files = fpga/soc_reset.vhdl \
+fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
 	fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
 	nonrandom.vhdl
 
-synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 
 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
-	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
+	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
 
 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
-	$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
+	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 
+# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
-	$(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel
+	verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
+	make -C obj_dir -f Vmicrowatt.mk
 	@cp -f obj_dir/microwatt-verilator microwatt-verilator
 
 microwatt_out.config: microwatt.json $(LPF)
@@ -247,36 +207,18 @@ microwatt_out.config: microwatt.json $(LPF)
 	mv -f $@.tmp $@
 
 microwatt.bit: microwatt_out.config
-	$(ECPPACK) --compress --freq 38.8 --svf microwatt.svf $< $@
+	$(ECPPACK) --svf microwatt.svf $< $@
 
 microwatt.svf: microwatt.bit
 
 prog: microwatt.svf
 	$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
 
-microwatt.dfu: microwatt.bit
-	cp $< $@.tmp
-	$(DFUSUFFIX) -v $(DFU_VENDOR) -p $(DFU_PRODUCT) -a $@.tmp
-	mv $@.tmp $@
-
-dfuprog: microwatt.dfu
-	$(DFUUTIL) -a 0 -D $<
-
-ecpprog: microwatt.bit
-	$(ECPPROG) -S $<
-
-ecpflash: microwatt.bit
-	test -n "$(ECP_FLASH_OFFSET)" || (echo Error: No ECP_FLASH_OFFSET defined for target; exit 1)
-	$(ECPPROG) -o $(ECP_FLASH_OFFSET) $<
-
 tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
 tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
 
 tests_console: $(tests_console)
 
-check_vunit:
-	$(VUNITRUN) $(VUNITARGS)
-
 check: $(tests) tests_console test_micropython test_micropython_long tests_unit
 
 check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
@@ -290,24 +232,22 @@ $(tests_console): core_tb
 test_micropython: core_tb
 	@./scripts/test_micropython.py
 
-test_micropython_verilator: microwatt-verilator
-	@./scripts/test_micropython_verilator.py
-
 test_micropython_long: core_tb
 	@./scripts/test_micropython_long.py
 
-test_micropython_verilator_long: microwatt-verilator
-	@./scripts/test_micropython_verilator_long.py
-
+tests_core_tb = $(patsubst %_tb,%_tb_test,$(core_tbs))
 tests_soc_tb = $(patsubst %_tb,%_tb_test,$(soc_tbs))
 
 %_test: %
 	./$< --assert-level=error > /dev/null
 
+tests_core: $(tests_core_tb)
+
 tests_soc: $(tests_soc_tb)
 
 # FIXME SOC tests have bit rotted, so disable for now
-#tests_unit: tests_soc
+#tests_unit: tests_core tests_soc
+tests_unit: tests_core
 
 TAGS:
 	find . -name '*.vhdl' | xargs ./scripts/vhdltags

README.md

@@ -97,19 +97,15 @@ sudo dnf copr enable sharkcz/danny
 sudo dnf install fusesoc
 ```
 
-- If this is your first time using fusesoc, initialize fusesoc. 
-  This is needed to be able to pull down fussoc library components referenced 
-  by microwatt. Run
+- Create a working directory and point FuseSoC at microwatt:
 
 ```
-fusesoc init
-fusesoc fetch uart16550
-fusesoc library add microwatt /path/to/microwatt
+mkdir microwatt-fusesoc
+cd microwatt-fusesoc
+fusesoc library add microwatt /path/to/microwatt/
 ```
 
 - Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
-  You may wish to ensure you have [installed Digilent Board files](https://reference.digilentinc.com/vivado/installing-vivado/start#installing_digilent_board_files) 
-  or appropriate files for your board first.
 
 ```
 fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
@@ -122,68 +118,6 @@ You should then be able to see output via the serial port of the board (/dev/tty
 fusesoc run --target=nexys_video microwatt
 ```
 
-## Linux on Microwatt
-
-Mainline Linux supports Microwatt as of v5.14. The Arty A7 is the best tested
-platform, but it's also been tested on the OrangeCrab and ButterStick.
-
-1. Use buildroot to create a userspace
-
-   A small change is required to glibc in order to support the VMX/AltiVec-less
-   Microwatt, as float128 support is mandiatory and for this in GCC requires
-   VSX/AltiVec. This change is included in Joel's buildroot fork, along with a
-   defconfig:
-   ```
-   git clone -b microwatt https://github.com/shenki/buildroot
-   cd buildroot
-   make ppc64le_microwatt_defconfig
-   make
-   ```
-
-   The output is `output/images/rootfs.cpio`.
-
-2. Build the Linux kernel
-   ```
-   git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
-   cd linux
-   make ARCH=powerpc microwatt_defconfig
-   make ARCH=powerpc CROSS_COMPILE=powerpc64le-linux-gnu- \
-     CONFIG_INITRAMFS_SOURCE=/buildroot/output/images/rootfs.cpio -j`nproc`
-   ```
-
-   The output is `arch/powerpc/boot/dtbImage.microwatt.elf`.
-
-3. Build gateware using FuseSoC
-
-   First configure FuseSoC as above.
-   ```
-   fusesoc run --build --target=arty_a7-100 microwatt --no_bram --memory_size=0
-   ```
-
-   The output is `build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit`.
-
-4. Program the flash
-
-   This operation will overwrite the contents of your flash.
-
-   For the Arty A7 A100, set `FLASH_ADDRESS` to `0x400000` and pass `-f a100`.
-
-   For the Arty A7 A35, set `FLASH_ADDRESS` to `0x300000` and pass `-f a35`.
-   ```
-   microwatt/openocd/flash-arty -f a100 build/microwatt_0/arty_a7-100-vivado/microwatt_0.bit
-   microwatt/openocd/flash-arty -f a100 dtbImage.microwatt.elf -t bin -a $FLASH_ADDRESS
-   ```
-
-5. Connect to the second USB TTY device exposed by the FPGA
-
-   ```
-   minicom -D /dev/ttyUSB1
-   ```
-
-   The gateware has firmware that will look at `FLASH_ADDRESS` and attempt to
-   parse an ELF there, loading it to the address specified in the ELF header
-   and jumping to it.
-
 ## Testing
 
 - A simple test suite containing random execution test cases and a couple of
@@ -195,5 +129,8 @@ make -j$(nproc) check
 
 ## Issues
 
-- There are a few instructions still to be implemented:
-  - Vector/VMX/VSX
+This is functional, but very simple. We still have quite a lot to do:
+
+- There are a few instructions still to be implemented
+- Need to add caches and bypassing (in progress)
+- Need to add supervisor state (in progress)

cache_ram.vhdl

@@ -5,21 +5,21 @@ use ieee.math_real.all;
 
 entity cache_ram is
     generic(
-        ROW_BITS : integer := 16;
-        WIDTH    : integer := 64;
-        TRACE    : boolean := false;
-        ADD_BUF  : boolean := false
-        );
+	ROW_BITS : integer := 16;
+	WIDTH    : integer := 64;
+	TRACE    : boolean := false;
+	ADD_BUF  : boolean := false
+	);
 
     port(
-        clk     : in  std_logic;
-        rd_en   : in  std_logic;
-        rd_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
-        rd_data : out std_logic_vector(WIDTH - 1 downto 0);
-        wr_sel  : in  std_logic_vector(WIDTH/8 - 1 downto 0);
-        wr_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
-        wr_data : in  std_logic_vector(WIDTH - 1 downto 0)
-        );
+	clk     : in  std_logic;
+	rd_en   : in  std_logic;
+	rd_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
+	rd_data : out std_logic_vector(WIDTH - 1 downto 0);
+	wr_sel  : in  std_logic_vector(WIDTH/8 - 1 downto 0);
+	wr_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
+	wr_data : in  std_logic_vector(WIDTH - 1 downto 0)
+	);
 
 end cache_ram;
 
@@ -35,13 +35,13 @@ architecture rtl of cache_ram is
 
 begin
     process(clk)
-        variable lbit : integer range 0 to WIDTH - 1;
-        variable mbit : integer range 0 to WIDTH - 1;
-        variable widx : integer range 0 to SIZE - 1;
-        constant sel0 : std_logic_vector(WIDTH/8 - 1 downto 0)
+	variable lbit : integer range 0 to WIDTH - 1;
+	variable mbit : integer range 0 to WIDTH - 1;
+	variable widx : integer range 0 to SIZE - 1;
+	constant sel0 : std_logic_vector(WIDTH/8 - 1 downto 0)
             := (others => '0');
     begin
-        if rising_edge(clk) then
+	if rising_edge(clk) then
             if TRACE then
                 if wr_sel /= sel0 then
                     report "write a:" & to_hstring(wr_addr) &
@@ -57,29 +57,29 @@ begin
                     ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
                 end if;
             end loop;
-            if rd_en = '1' then
-                rd_data0 <= ram(to_integer(unsigned(rd_addr)));
-                if TRACE then
-                    report "read a:" & to_hstring(rd_addr) &
-                        " dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
-                end if;
-            end if;
-        end if;
+	    if rd_en = '1' then
+		rd_data0 <= ram(to_integer(unsigned(rd_addr)));
+		if TRACE then
+		    report "read a:" & to_hstring(rd_addr) &
+			" dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
+		end if;
+	    end if;
+	end if;
     end process;
 
     buf: if ADD_BUF generate
     begin
-        process(clk)
-        begin
-            if rising_edge(clk) then
-                rd_data <= rd_data0;
-            end if;
-        end process;
+	process(clk)
+	begin
+	    if rising_edge(clk) then
+		rd_data <= rd_data0;
+	    end if;
+	end process;
     end generate;
 
     nobuf: if not ADD_BUF generate
     begin
-        rd_data <= rd_data0;
+	rd_data <= rd_data0;
     end generate;
 
 end;

common.vhdl

@@ -21,7 +21,6 @@ package common is
     constant MSR_FE1 : integer := (63 - 55);    -- Floating Exception mode
     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
-    constant MSR_PMM : integer := (63 - 61);    -- Performance Monitor Mark
     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
 
@@ -52,37 +51,9 @@ package common is
     constant SPR_HSPRG0 : spr_num_t := 304;
     constant SPR_HSPRG1 : spr_num_t := 305;
     constant SPR_PID    : spr_num_t := 48;
-    constant SPR_PTCR   : spr_num_t := 464;
+    constant SPR_PRTBL  : spr_num_t := 720;
     constant SPR_PVR	: spr_num_t := 287;
 
-    -- PMU registers
-    constant SPR_UPMC1  : spr_num_t := 771;
-    constant SPR_UPMC2  : spr_num_t := 772;
-    constant SPR_UPMC3  : spr_num_t := 773;
-    constant SPR_UPMC4  : spr_num_t := 774;
-    constant SPR_UPMC5  : spr_num_t := 775;
-    constant SPR_UPMC6  : spr_num_t := 776;
-    constant SPR_UMMCR0 : spr_num_t := 779;
-    constant SPR_UMMCR1 : spr_num_t := 782;
-    constant SPR_UMMCR2 : spr_num_t := 769;
-    constant SPR_UMMCRA : spr_num_t := 770;
-    constant SPR_USIER  : spr_num_t := 768;
-    constant SPR_USIAR  : spr_num_t := 780;
-    constant SPR_USDAR  : spr_num_t := 781;
-    constant SPR_PMC1   : spr_num_t := 787;
-    constant SPR_PMC2   : spr_num_t := 788;
-    constant SPR_PMC3   : spr_num_t := 789;
-    constant SPR_PMC4   : spr_num_t := 790;
-    constant SPR_PMC5   : spr_num_t := 791;
-    constant SPR_PMC6   : spr_num_t := 792;
-    constant SPR_MMCR0  : spr_num_t := 795;
-    constant SPR_MMCR1  : spr_num_t := 798;
-    constant SPR_MMCR2  : spr_num_t := 785;
-    constant SPR_MMCRA  : spr_num_t := 786;
-    constant SPR_SIER   : spr_num_t := 784;
-    constant SPR_SIAR   : spr_num_t := 796;
-    constant SPR_SDAR   : spr_num_t := 797;
-
     -- GPR indices in the register file (GPR only)
     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
 
@@ -156,12 +127,6 @@ package common is
     constant FPSCR_NI     : integer := 63 - 61;
     constant FPSCR_RN     : integer := 63 - 63;
 
-    -- Real addresses
-    -- REAL_ADDR_BITS is the number of real address bits that we store
-    constant REAL_ADDR_BITS : positive := 56;
-    subtype real_addr_t is std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
-    function addr_to_real(addr: std_ulogic_vector(63 downto 0)) return real_addr_t;
-
     -- Used for tracking instruction completion and pending register writes
     constant TAG_COUNT : positive := 4;
     constant TAG_NUMBER_BITS : natural := log2(TAG_COUNT);
@@ -200,8 +165,8 @@ package common is
         priv_mode : std_ulogic;
         big_endian : std_ulogic;
 	stop_mark: std_ulogic;
+        sequential: std_ulogic;
         predicted : std_ulogic;
-        pred_ntaken : std_ulogic;
 	nia: std_ulogic_vector(63 downto 0);
     end record;
 
@@ -213,12 +178,6 @@ package common is
 	insn: std_ulogic_vector(31 downto 0);
         big_endian: std_ulogic;
         next_predicted: std_ulogic;
-        next_pred_ntaken: std_ulogic;
-    end record;
-
-    type IcacheEventType is record
-        icache_miss : std_ulogic;
-        itlb_miss_resolved : std_ulogic;
     end record;
 
     type Decode1ToDecode2Type is record
@@ -344,51 +303,6 @@ package common is
                                                               is_extended => '0', is_modulus => '0',
                                                               neg_result => '0', others => (others => '0'));
 
-    type PMUEventType is record
-        no_instr_avail      : std_ulogic;
-        dispatch            : std_ulogic;
-        ext_interrupt       : std_ulogic;
-        instr_complete      : std_ulogic;
-        fp_complete         : std_ulogic;
-        ld_complete         : std_ulogic;
-        st_complete         : std_ulogic;
-        br_taken_complete   : std_ulogic;
-        br_mispredict       : std_ulogic;
-        ipref_discard       : std_ulogic;
-        itlb_miss           : std_ulogic;
-        itlb_miss_resolved  : std_ulogic;
-        icache_miss         : std_ulogic;
-        dc_miss_resolved    : std_ulogic;
-        dc_load_miss        : std_ulogic;
-        dc_ld_miss_resolved : std_ulogic;
-        dc_store_miss       : std_ulogic;
-        dtlb_miss           : std_ulogic;
-        dtlb_miss_resolved  : std_ulogic;
-        ld_miss_nocache     : std_ulogic;
-        ld_fill_nocache     : std_ulogic;
-    end record;
-    constant PMUEventInit : PMUEventType := (others => '0');
-
-    type Execute1ToPMUType is record
-        mfspr   : std_ulogic;
-        mtspr   : std_ulogic;
-        spr_num : std_ulogic_vector(4 downto 0);
-        spr_val : std_ulogic_vector(63 downto 0);
-        tbbits  : std_ulogic_vector(3 downto 0);        -- event bits from timebase
-        pmm_msr : std_ulogic;                           -- PMM bit from MSR
-        pr_msr  : std_ulogic;                           -- PR bit from MSR
-        run     : std_ulogic;
-        nia     : std_ulogic_vector(63 downto 0);
-        addr    : std_ulogic_vector(63 downto 0);
-        addr_v  : std_ulogic;
-        occur   : PMUEventType;
-    end record;
-
-    type PMUToExecute1Type is record
-        spr_val : std_ulogic_vector(63 downto 0);
-        intr    : std_ulogic;
-    end record;
-
     type Decode2ToRegisterFileType is record
 	read1_enable : std_ulogic;
 	read1_reg : gspr_index_t;
@@ -455,7 +369,6 @@ package common is
     type Loadstore1ToExecute1Type is record
         busy : std_ulogic;
         in_progress : std_ulogic;
-        interrupt : std_ulogic;
     end record;
 
     type Loadstore1ToDcacheType is record
@@ -482,14 +395,6 @@ package common is
         cache_paradox : std_ulogic;
     end record;
 
-    type DcacheEventType is record
-        load_miss          : std_ulogic;
-        store_miss         : std_ulogic;
-        dcache_refill      : std_ulogic;
-        dtlb_miss          : std_ulogic;
-        dtlb_miss_resolved : std_ulogic;
-    end record;
-
     type Loadstore1ToMmuType is record
         valid : std_ulogic;
         tlbie : std_ulogic;
@@ -559,12 +464,6 @@ package common is
          interrupt => '0', intr_vec => 0,
          srr0 => (others => '0'), srr1 => (others => '0'));
 
-    type Loadstore1EventType is record
-        load_complete  : std_ulogic;
-        store_complete : std_ulogic;
-        itlb_miss      : std_ulogic;
-    end record;
-
     type Execute1ToWritebackType is record
 	valid: std_ulogic;
         instr_tag : instr_tag_t;
@@ -695,11 +594,6 @@ package common is
 							       write_cr_mask => (others => '0'),
 							       write_cr_data => (others => '0'));
 
-    type WritebackEventType is record
-        instr_complete : std_ulogic;
-        fp_complete    : std_ulogic;
-    end record;
-
 end common;
 
 package body common is
@@ -784,9 +678,4 @@ package body common is
     begin
         return tag1.valid = '1' and tag2.valid = '1' and tag1.tag = tag2.tag;
     end;
-
-    function addr_to_real(addr: std_ulogic_vector(63 downto 0)) return real_addr_t is
-    begin
-        return addr(real_addr_t'range);
-    end;
 end common;

constraints/orange-crab-0.2.lpf

@@ -1,225 +0,0 @@
-LOCATE COMP "ext_clk" SITE "A9";
-IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33;
-
-// LOCATE COMP "ext_rst_n" SITE "J2"; // io_13
-// IOBUF PORT "ext_rst_n" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
-
-// user_button as reset
-LOCATE COMP "ext_rst_n" SITE "J17";
-IOBUF PORT "ext_rst_n" IO_TYPE=SSTL135_I;
-
-LOCATE COMP "usb_d_p" SITE "N1";
-LOCATE COMP "usb_d_n" SITE "M2";
-LOCATE COMP "usb_pullup" SITE "N2";
-
-IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33;
-IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33;
-IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33;
-
-LOCATE COMP "led0_g" SITE "M3";
-LOCATE COMP "led0_r" SITE "K4";
-LOCATE COMP "led0_b" SITE "J3";
-
-IOBUF PORT "led0_g" IO_TYPE=LVCMOS33;
-IOBUF PORT "led0_g" IO_TYPE=LVCMOS33;
-IOBUF PORT "led0_b" IO_TYPE=LVCMOS33;
-
-// discontinuous gpio numbers, match orangecrab litex platform
-LOCATE COMP "pin_gpio_0" SITE "N17"; // tx
-LOCATE COMP "pin_gpio_1" SITE "M18"; // rx
-LOCATE COMP "pin_gpio_2" SITE "C10"; // sda
-LOCATE COMP "pin_gpio_3" SITE "C9"; // scl
-//
-LOCATE COMP "pin_gpio_5" SITE "B10"; // io_5
-LOCATE COMP "pin_gpio_6" SITE "B9"; // ...
-//
-LOCATE COMP "pin_gpio_9" SITE "C8"; //
-LOCATE COMP "pin_gpio_10" SITE "B8"; //
-LOCATE COMP "pin_gpio_11" SITE "A8"; //
-LOCATE COMP "pin_gpio_12" SITE "H2"; //
-LOCATE COMP "pin_gpio_13" SITE "J2"; // io_13
-LOCATE COMP "pin_gpio_14" SITE "N15"; // miso
-LOCATE COMP "pin_gpio_15" SITE "R17"; // sck
-LOCATE COMP "pin_gpio_16" SITE "N16"; // mosi
-
-LOCATE COMP "pin_io_a0" SITE "L4";
-LOCATE COMP "pin_io_a1" SITE "N3";
-LOCATE COMP "pin_io_a2" SITE "N4";
-LOCATE COMP "pin_io_a3" SITE "H4";
-LOCATE COMP "pin_io_a4" SITE "G4";
-LOCATE COMP "pin_io_a5" SITE "T17";
-
-IOBUF PORT "pin_gpio_0" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_1" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_2" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_3" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_5" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_6" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_9" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_10" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_11" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_12" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_13" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_14" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_15" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_gpio_16" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_io_a0" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_io_a1" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_io_a2" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_io_a3" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_io_a4" IO_TYPE=LVCMOS33;
-IOBUF PORT "pin_io_a5" IO_TYPE=LVCMOS33;
-
-LOCATE COMP "ddram_a[0]"  SITE "C4";
-LOCATE COMP "ddram_a[1]"  SITE "D2";
-LOCATE COMP "ddram_a[2]"  SITE "D3";
-LOCATE COMP "ddram_a[3]"  SITE "A3";
-LOCATE COMP "ddram_a[4]"  SITE "A4";
-LOCATE COMP "ddram_a[5]"  SITE "D4";
-LOCATE COMP "ddram_a[6]"  SITE "C3";
-LOCATE COMP "ddram_a[7]"  SITE "B2";
-LOCATE COMP "ddram_a[8]"  SITE "B1";
-LOCATE COMP "ddram_a[9]"  SITE "D1";
-LOCATE COMP "ddram_a[10]" SITE "A7";
-LOCATE COMP "ddram_a[11]" SITE "C2";
-LOCATE COMP "ddram_a[12]" SITE "B6";
-LOCATE COMP "ddram_a[13]" SITE "C1";
-LOCATE COMP "ddram_a[14]" SITE "A2";
-LOCATE COMP "ddram_a[15]" SITE "C7";
-IOBUF PORT "ddram_a[0]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[1]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[2]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[3]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[4]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[5]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[6]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[7]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[8]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[9]"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-
-LOCATE COMP "ddram_ba[0]" SITE "D6";
-LOCATE COMP "ddram_ba[1]" SITE "B7";
-LOCATE COMP "ddram_ba[2]" SITE "A6";
-LOCATE COMP "ddram_cas_n" SITE "D13";
-LOCATE COMP "ddram_cs_n"  SITE "A12";
-LOCATE COMP "ddram_dm[0]" SITE "D16";
-LOCATE COMP "ddram_dm[1]" SITE "G16";
-LOCATE COMP "ddram_ras_n" SITE "C12";
-LOCATE COMP "ddram_we_n"  SITE "B12";
-IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_cs_n"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_we_n"  IO_TYPE=SSTL135_I SLEWRATE=FAST;
-
-// from litex platform, termination disabled to reduce heat
-LOCATE COMP "ddram_dq[0]"  SITE "C17";
-LOCATE COMP "ddram_dq[1]"  SITE "D15";
-LOCATE COMP "ddram_dq[2]"  SITE "B17";
-LOCATE COMP "ddram_dq[3]"  SITE "C16";
-LOCATE COMP "ddram_dq[4]"  SITE "A15";
-LOCATE COMP "ddram_dq[5]"  SITE "B13";
-LOCATE COMP "ddram_dq[6]"  SITE "A17";
-LOCATE COMP "ddram_dq[7]"  SITE "A13";
-LOCATE COMP "ddram_dq[8]"  SITE "F17";
-LOCATE COMP "ddram_dq[9]"  SITE "F16";
-LOCATE COMP "ddram_dq[10]" SITE "G15";
-LOCATE COMP "ddram_dq[11]" SITE "F15";
-LOCATE COMP "ddram_dq[12]" SITE "J16";
-LOCATE COMP "ddram_dq[13]" SITE "C18";
-LOCATE COMP "ddram_dq[14]" SITE "H16";
-LOCATE COMP "ddram_dq[15]" SITE "F18";
-IOBUF PORT "ddram_dq[0]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[1]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[2]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[3]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[4]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[5]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[6]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[7]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[8]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[9]"  IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
-
-LOCATE COMP "ddram_dqs_n[0]" SITE "A16";
-LOCATE COMP "ddram_dqs_n[1]" SITE "H17";
-LOCATE COMP "ddram_dqs_p[0]" SITE "B15";
-LOCATE COMP "ddram_dqs_p[1]" SITE "G18";
-IOBUF PORT "ddram_dqs_n[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
-IOBUF PORT "ddram_dqs_n[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
-IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
-IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
-
-LOCATE COMP "ddram_clk_p" SITE "J18";
-LOCATE COMP "ddram_clk_n" SITE "K18";
-IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I SLEWRATE=FAST;
-IOBUF PORT "ddram_clk_n" IO_TYPE=SSTL135D_I SLEWRATE=FAST;
-
-LOCATE COMP "ddram_cke"     SITE "D18";
-LOCATE COMP "ddram_odt"     SITE "C13";
-LOCATE COMP "ddram_reset_n" SITE "L18";
-IOBUF PORT "ddram_cke"     IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_odt"     IO_TYPE=SSTL135_I SLEWRATE=FAST;
-IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
-
-LOCATE COMP "ddram_vccio[0]" SITE "K16";
-LOCATE COMP "ddram_vccio[1]" SITE "D17";
-LOCATE COMP "ddram_vccio[2]" SITE "K15";
-LOCATE COMP "ddram_vccio[3]" SITE "K17";
-LOCATE COMP "ddram_vccio[4]" SITE "B18";
-LOCATE COMP "ddram_vccio[5]" SITE "C6";
-LOCATE COMP "ddram_gnd[0]"   SITE "L15";
-LOCATE COMP "ddram_gnd[1]"   SITE "L16";
-IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
-IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
-IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
-IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
-IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
-IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
-IOBUF PORT "ddram_gnd[0]"   IO_TYPE=SSTL135_II SLEWRATE=FAST;
-IOBUF PORT "ddram_gnd[1]"   IO_TYPE=SSTL135_II SLEWRATE=FAST;
-
-// We use USRMCLK instead for clk
-// LOCATE COMP "spi_flash_clk" SITE "U16";
-// IOBUF PORT "spi_flash_clk" IO_TYPE=LVCMOS33;
-LOCATE COMP "spi_flash_cs_n" SITE "U17";
-IOBUF PORT "spi_flash_cs_n" IO_TYPE=LVCMOS33;
-LOCATE COMP "spi_flash_mosi" SITE "U18";
-IOBUF PORT "spi_flash_mosi" IO_TYPE=LVCMOS33;
-LOCATE COMP "spi_flash_miso" SITE "T18";
-IOBUF PORT "spi_flash_miso" IO_TYPE=LVCMOS33;
-LOCATE COMP "spi_flash_wp_n" SITE "R18";
-IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33;
-LOCATE COMP "spi_flash_hold_n" SITE "N18";
-IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33;
-
-LOCATE COMP "sdcard_data[0]" SITE "J1";
-LOCATE COMP "sdcard_data[1]" SITE "K3";
-LOCATE COMP "sdcard_data[2]" SITE "L3";
-LOCATE COMP "sdcard_data[3]" SITE "M1";
-LOCATE COMP "sdcard_cmd" SITE "K2";
-LOCATE COMP "sdcard_clk" SITE "K1";
-LOCATE COMP "sdcard_cd" SITE "L1";
-
-IOBUF PORT "sdcard_data[0]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
-IOBUF PORT "sdcard_data[1]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
-IOBUF PORT "sdcard_data[2]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
-IOBUF PORT "sdcard_data[3]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
-IOBUF PORT "sdcard_cmd" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
-IOBUF PORT "sdcard_clk" IO_TYPE=LVCMOS33 SLEWRATE=FAST;
-IOBUF PORT "sdcard_cd" IO_TYPE=LVCMOS33;

control.vhdl

@@ -17,7 +17,7 @@ entity control is
         valid_in            : in std_ulogic;
         repeated            : in std_ulogic;
         flush_in            : in std_ulogic;
-        busy_in             : in std_ulogic;
+	busy_in             : in std_ulogic;
         deferred            : in std_ulogic;
         sgl_pipe_in         : in std_ulogic;
         stop_mark_in        : in std_ulogic;
@@ -64,8 +64,8 @@ architecture rtl of control is
 
     signal r_int, rin_int : reg_internal_type := reg_internal_init;
 
-    signal gpr_write_valid : std_ulogic;
-    signal cr_write_valid  : std_ulogic;
+    signal gpr_write_valid : std_ulogic := '0';
+    signal cr_write_valid  : std_ulogic := '0';
 
     type tag_register is record
         wr_gpr : std_ulogic;
@@ -245,8 +245,6 @@ begin
         end if;
 
         if rst = '1' then
-            gpr_write_valid <= '0';
-            cr_write_valid <= '0';
             v_int := reg_internal_init;
             valid_tmp := '0';
         end if;

core.vhdl

@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 library work;
+use work.params.all;
 use work.common.all;
 use work.wishbone_types.all;
 
@@ -13,16 +14,9 @@ entity core is
         EX1_BYPASS : boolean := true;
         HAS_FPU : boolean := true;
         HAS_BTC : boolean := true;
-        HAS_SHORT_MULT : boolean := false;
 	ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
         LOG_LENGTH : natural := 512;
-        ICACHE_NUM_LINES : natural := 64;
-        ICACHE_NUM_WAYS : natural := 2;
-        ICACHE_TLB_SIZE : natural := 64;
-        DCACHE_NUM_LINES : natural := 64;
-        DCACHE_NUM_WAYS : natural := 2;
-        DCACHE_TLB_SET_SIZE : natural := 64;
-        DCACHE_TLB_NUM_WAYS : natural := 2
+        CACHE_PARAMS : CACHE_PARAMS_T := CACHE_PARAMS_DEFAULT
         );
     port (
         clk          : in std_ulogic;
@@ -38,8 +32,6 @@ entity core is
         wishbone_data_in  : in wishbone_slave_out;
         wishbone_data_out : out wishbone_master_out;
 
-        wb_snoop_in     : in wishbone_master_out;
-
 	dmi_addr	: in std_ulogic_vector(3 downto 0);
 	dmi_din	        : in std_ulogic_vector(63 downto 0);
 	dmi_dout	: out std_ulogic_vector(63 downto 0);
@@ -117,20 +109,21 @@ architecture behave of core is
     signal complete: instr_tag_t;
     signal terminate: std_ulogic;
     signal core_rst: std_ulogic;
+    signal icache_inv: std_ulogic;
     signal do_interrupt: std_ulogic;
 
     -- Delayed/Latched resets and alt_reset
-    signal rst_fetch1  : std_ulogic;
-    signal rst_fetch2  : std_ulogic;
-    signal rst_icache  : std_ulogic;
-    signal rst_dcache  : std_ulogic;
-    signal rst_dec1    : std_ulogic;
-    signal rst_dec2    : std_ulogic;
-    signal rst_ex1     : std_ulogic;
-    signal rst_fpu     : std_ulogic;
-    signal rst_ls1     : std_ulogic;
-    signal rst_wback   : std_ulogic;
-    signal rst_dbg     : std_ulogic;
+    signal rst_fetch1  : std_ulogic := '1';
+    signal rst_fetch2  : std_ulogic := '1';
+    signal rst_icache  : std_ulogic := '1';
+    signal rst_dcache  : std_ulogic := '1';
+    signal rst_dec1    : std_ulogic := '1';
+    signal rst_dec2    : std_ulogic := '1';
+    signal rst_ex1     : std_ulogic := '1';
+    signal rst_fpu     : std_ulogic := '1';
+    signal rst_ls1     : std_ulogic := '1';
+    signal rst_wback   : std_ulogic := '1';
+    signal rst_dbg     : std_ulogic := '1';
     signal alt_reset_d : std_ulogic;
 
     signal sim_cr_dump: std_ulogic;
@@ -147,12 +140,6 @@ architecture behave of core is
 
     signal msr : std_ulogic_vector(63 downto 0);
 
-    -- PMU event bus
-    signal icache_events    : IcacheEventType;
-    signal loadstore_events : Loadstore1EventType;
-    signal dcache_events    : DcacheEventType;
-    signal writeback_events : WritebackEventType;
-
     -- Debug status
     signal dbg_core_is_stopped: std_ulogic;
 
@@ -231,10 +218,10 @@ begin
     icache_0: entity work.icache
         generic map(
             SIM => SIM,
-            LINE_SIZE => 64,
-            NUM_LINES => ICACHE_NUM_LINES,
-            NUM_WAYS => ICACHE_NUM_WAYS,
-            TLB_SIZE => ICACHE_TLB_SIZE,
+            LINE_SIZE => CACHE_PARAMS.LINE_SIZE,
+            NUM_LINES => CACHE_PARAMS.ICACHE_NUM_LINES,
+            NUM_WAYS => CACHE_PARAMS.ICACHE_NUM_WAYS,
+            TLB_SIZE => CACHE_PARAMS.ICACHE_TLB_SIZE,
             LOG_LENGTH => LOG_LENGTH
             )
         port map(
@@ -249,8 +236,6 @@ begin
 	    stall_out => icache_stall_out,
             wishbone_out => wishbone_insn_out,
             wishbone_in => wishbone_insn_in,
-            wb_snoop_in => wb_snoop_in,
-            events => icache_events,
             log_out => log_data(96 downto 43)
             );
 
@@ -340,7 +325,6 @@ begin
         generic map (
             EX1_BYPASS => EX1_BYPASS,
             HAS_FPU => HAS_FPU,
-            HAS_SHORT_MULT => HAS_SHORT_MULT,
             LOG_LENGTH => LOG_LENGTH
             )
         port map (
@@ -360,10 +344,6 @@ begin
             bypass_cr_data => execute1_cr_bypass,
 	    icache_inval => ex1_icache_inval,
             dbg_msr_out => msr,
-            wb_events => writeback_events,
-            ls_events => loadstore_events,
-            dc_events => dcache_events,
-            ic_events => icache_events,
             terminate_out => terminate,
             log_out => log_data(134 downto 120),
             log_rd_addr => log_rd_addr,
@@ -405,7 +385,6 @@ begin
             m_out => loadstore1_to_mmu,
             m_in => mmu_to_loadstore1,
             dc_stall => dcache_stall_out,
-            events => loadstore_events,
             log_out => log_data(149 downto 140)
             );
 
@@ -422,11 +401,11 @@ begin
 
     dcache_0: entity work.dcache
         generic map(
-            LINE_SIZE => 64,
-            NUM_LINES => DCACHE_NUM_LINES,
-            NUM_WAYS => DCACHE_NUM_WAYS,
-            TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
-            TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS,
+            LINE_SIZE => CACHE_PARAMS.LINE_SIZE,
+            NUM_LINES => CACHE_PARAMS.DCACHE_NUM_LINES,
+            NUM_WAYS => CACHE_PARAMS.DCACHE_NUM_WAYS,
+            TLB_SET_SIZE => CACHE_PARAMS.DCACHE_TLB_SET_SIZE,
+            TLB_NUM_WAYS => CACHE_PARAMS.DCACHE_TLB_NUM_WAYS,
             LOG_LENGTH => LOG_LENGTH
             )
         port map (
@@ -439,8 +418,6 @@ begin
             stall_out => dcache_stall_out,
             wishbone_in => wishbone_data_in,
             wishbone_out => wishbone_data_out,
-            snoop_in => wb_snoop_in,
-            events => dcache_events,
             log_out => log_data(170 downto 151)
             );
 
@@ -455,7 +432,6 @@ begin
             w_out => writeback_to_register_file,
             c_out => writeback_to_cr_file,
             f_out => writeback_to_fetch1,
-            events => writeback_events,
             interrupt_out => do_interrupt,
             complete_out => complete
             );

core_debug.vhdl

@@ -12,25 +12,25 @@ entity core_debug is
         LOG_LENGTH : natural := 512
         );
     port (
-        clk             : in std_logic;
-        rst             : in std_logic;
-
-        dmi_addr        : in std_ulogic_vector(3 downto 0);
-        dmi_din         : in std_ulogic_vector(63 downto 0);
-        dmi_dout        : out std_ulogic_vector(63 downto 0);
-        dmi_req         : in std_ulogic;
-        dmi_wr          : in std_ulogic;
-        dmi_ack         : out std_ulogic;
-
-        -- Debug actions
-        core_stop       : out std_ulogic;
-        core_rst        : out std_ulogic;
-        icache_rst      : out std_ulogic;
-
-        -- Core status inputs
-        terminate       : in std_ulogic;
-        core_stopped    : in std_ulogic;
-        nia             : in std_ulogic_vector(63 downto 0);
+        clk          : in std_logic;
+        rst          : in std_logic;
+
+	dmi_addr	: in std_ulogic_vector(3 downto 0);
+	dmi_din	        : in std_ulogic_vector(63 downto 0);
+	dmi_dout	: out std_ulogic_vector(63 downto 0);
+	dmi_req	        : in std_ulogic;
+	dmi_wr		: in std_ulogic;
+	dmi_ack	        : out std_ulogic;
+
+	-- Debug actions
+	core_stop       : out std_ulogic;
+	core_rst        : out std_ulogic;
+	icache_rst      : out std_ulogic;
+
+	-- Core status inputs
+	terminate       : in std_ulogic;
+	core_stopped    : in std_ulogic;
+	nia             : in std_ulogic_vector(63 downto 0);
         msr             : in std_ulogic_vector(63 downto 0);
 
         -- GSPR register read port
@@ -45,8 +45,8 @@ entity core_debug is
         log_read_data   : out std_ulogic_vector(63 downto 0);
         log_write_addr  : out std_ulogic_vector(31 downto 0);
 
-        -- Misc
-        terminated_out  : out std_ulogic
+	-- Misc
+	terminated_out  : out std_ulogic
         );
 end core_debug;
 
@@ -60,7 +60,7 @@ architecture behave of core_debug is
     -- bit     2 : Icache reset
     -- bit     3 : Single step
     -- bit     4 : Core start
-    constant DBG_CORE_CTRL         : std_ulogic_vector(3 downto 0) := "0000";
+    constant DBG_CORE_CTRL	   : std_ulogic_vector(3 downto 0) := "0000";
     constant DBG_CORE_CTRL_STOP    : integer := 0;
     constant DBG_CORE_CTRL_RESET   : integer := 1;
     constant DBG_CORE_CTRL_ICRESET : integer := 2;
@@ -71,13 +71,13 @@ architecture behave of core_debug is
     -- bit    0 : Core stopping (wait til bit 1 set)
     -- bit    1 : Core stopped
     -- bit    2 : Core terminated (clears with start or reset)
-    constant DBG_CORE_STAT           : std_ulogic_vector(3 downto 0) := "0001";
+    constant DBG_CORE_STAT	   : std_ulogic_vector(3 downto 0) := "0001";
     constant DBG_CORE_STAT_STOPPING  : integer := 0;
     constant DBG_CORE_STAT_STOPPED   : integer := 1;
     constant DBG_CORE_STAT_TERM      : integer := 2;
 
     -- NIA register (read only for now)
-    constant DBG_CORE_NIA             : std_ulogic_vector(3 downto 0) := "0010";
+    constant DBG_CORE_NIA	     : std_ulogic_vector(3 downto 0) := "0010";
 
     -- MSR (read only)
     constant DBG_CORE_MSR            : std_ulogic_vector(3 downto 0) := "0011";
@@ -107,14 +107,14 @@ architecture behave of core_debug is
     signal do_gspr_rd   : std_ulogic;
     signal gspr_index   : gspr_index_t;
 
-    signal log_dmi_addr        : std_ulogic_vector(31 downto 0) := (others => '0');
-    signal log_dmi_data        : std_ulogic_vector(63 downto 0) := (others => '0');
-    signal log_dmi_trigger     : std_ulogic_vector(63 downto 0) := (others => '0');
-    signal do_log_trigger      : std_ulogic := '0';
-    signal do_dmi_log_rd       : std_ulogic;
-    signal dmi_read_log_data   : std_ulogic;
+    signal log_dmi_addr : std_ulogic_vector(31 downto 0) := (others => '0');
+    signal log_dmi_data : std_ulogic_vector(63 downto 0) := (others => '0');
+    signal log_dmi_trigger : std_ulogic_vector(63 downto 0) := (others => '0');
+    signal do_log_trigger : std_ulogic := '0';
+    signal do_dmi_log_rd : std_ulogic;
+    signal dmi_read_log_data : std_ulogic;
     signal dmi_read_log_data_1 : std_ulogic;
-    signal log_trigger_delay   : integer range 0 to 255 := 0;
+    signal log_trigger_delay : integer range 0 to 255 := 0;
 
 begin
        -- Single cycle register accesses on DMI except for GSPR data
@@ -125,37 +125,36 @@ begin
 
     -- Status register read composition
     stat_reg <= (2 => terminated,
-                 1 => core_stopped,
-                 0 => stopping,
-                 others => '0');
+		 1 => core_stopped,
+		 0 => stopping,
+		 others => '0');
 
     -- DMI read data mux
     with dmi_addr select dmi_dout <=
-        stat_reg        when DBG_CORE_STAT,
-        nia             when DBG_CORE_NIA,
+	stat_reg        when DBG_CORE_STAT,
+	nia             when DBG_CORE_NIA,
         msr             when DBG_CORE_MSR,
         dbg_gpr_data    when DBG_CORE_GSPR_DATA,
         log_write_addr & log_dmi_addr when DBG_CORE_LOG_ADDR,
         log_dmi_data    when DBG_CORE_LOG_DATA,
         log_dmi_trigger when DBG_CORE_LOG_TRIGGER,
-        (others => '0') when others;
+	(others => '0') when others;
 
     -- DMI writes
     reg_write: process(clk)
     begin
-        if rising_edge(clk) then
-            -- Reset the 1-cycle "do" signals
-            do_step <= '0';
-            do_reset <= '0';
-            do_icreset <= '0';
+	if rising_edge(clk) then
+	    -- Reset the 1-cycle "do" signals
+	    do_step <= '0';
+	    do_reset <= '0';
+	    do_icreset <= '0';
             do_dmi_log_rd <= '0';
 
-            if (rst) then
-                stopping <= '0';
-                terminated <= '0';
+	    if (rst) then
+		stopping <= '0';
+		terminated <= '0';
                 log_trigger_delay <= 0;
-                gspr_index <= (others => '0');
-            else
+	    else
                 if do_log_trigger = '1' or log_trigger_delay /= 0 then
                     if log_trigger_delay = 255 then
                         log_dmi_trigger(1) <= '1';
@@ -164,32 +163,32 @@ begin
                         log_trigger_delay <= log_trigger_delay + 1;
                     end if;
                 end if;
-                -- Edge detect on dmi_req for 1-shot pulses
-                dmi_req_1 <= dmi_req;
-                if dmi_req = '1' and dmi_req_1 = '0' then
-                    if dmi_wr = '1' then
-                        report("DMI write to " & to_hstring(dmi_addr));
-
-                        -- Control register actions
-                        if dmi_addr = DBG_CORE_CTRL then
-                            if dmi_din(DBG_CORE_CTRL_RESET) = '1' then
-                                do_reset <= '1';
-                                terminated <= '0';
-                            end if;
-                            if dmi_din(DBG_CORE_CTRL_STOP) = '1' then
-                                stopping <= '1';
-                            end if;
-                            if dmi_din(DBG_CORE_CTRL_STEP) = '1' then
-                                do_step <= '1';
-                                terminated <= '0';
-                            end if;
-                            if dmi_din(DBG_CORE_CTRL_ICRESET) = '1' then
-                                do_icreset <= '1';
-                            end if;
-                            if dmi_din(DBG_CORE_CTRL_START) = '1' then
-                                stopping <= '0';
-                                terminated <= '0';
-                            end if;
+		-- Edge detect on dmi_req for 1-shot pulses
+		dmi_req_1 <= dmi_req;
+		if dmi_req = '1' and dmi_req_1 = '0' then
+		    if dmi_wr = '1' then
+			report("DMI write to " & to_hstring(dmi_addr));
+
+			-- Control register actions
+			if dmi_addr = DBG_CORE_CTRL then
+			    if dmi_din(DBG_CORE_CTRL_RESET) = '1' then
+				do_reset <= '1';
+				terminated <= '0';
+			    end if;
+			    if dmi_din(DBG_CORE_CTRL_STOP) = '1' then
+				stopping <= '1';
+			    end if;
+			    if dmi_din(DBG_CORE_CTRL_STEP) = '1' then
+				do_step <= '1';
+				terminated <= '0';
+			    end if;
+			    if dmi_din(DBG_CORE_CTRL_ICRESET) = '1' then
+				do_icreset <= '1';
+			    end if;
+			    if dmi_din(DBG_CORE_CTRL_START) = '1' then
+				stopping <= '0';
+				terminated <= '0';
+			    end if;
                         elsif dmi_addr = DBG_CORE_GSPR_INDEX then
                             gspr_index <= dmi_din(gspr_index_t'left downto 0);
                         elsif dmi_addr = DBG_CORE_LOG_ADDR then
@@ -197,17 +196,17 @@ begin
                             do_dmi_log_rd <= '1';
                         elsif dmi_addr = DBG_CORE_LOG_TRIGGER then
                             log_dmi_trigger <= dmi_din;
-                        end if;
-                    else
-                        report("DMI read from " & to_string(dmi_addr));
-                    end if;
+			end if;
+		    else
+			report("DMI read from " & to_string(dmi_addr));
+		    end if;
 
                 elsif dmi_read_log_data = '0' and dmi_read_log_data_1 = '1' then
                     -- Increment log_dmi_addr after the end of a read from DBG_CORE_LOG_DATA
                     log_dmi_addr(LOG_INDEX_BITS + 1 downto 0) <=
                         std_ulogic_vector(unsigned(log_dmi_addr(LOG_INDEX_BITS+1 downto 0)) + 1);
                     do_dmi_log_rd <= '1';
-                end if;
+		end if;
                 dmi_read_log_data_1 <= dmi_read_log_data;
                 if dmi_req = '1' and dmi_addr = DBG_CORE_LOG_DATA then
                     dmi_read_log_data <= '1';
@@ -215,15 +214,15 @@ begin
                     dmi_read_log_data <= '0';
                 end if;
 
-                -- Set core stop on terminate. We'll be stopping some time *after*
-                -- the offending instruction, at least until we can do back flushes
-                -- that preserve NIA which we can't just yet.
-                if terminate = '1' then
-                    stopping <= '1';
-                    terminated <= '1';
-                end if;
-            end if;
-        end if;
+		-- Set core stop on terminate. We'll be stopping some time *after*
+		-- the offending instruction, at least until we can do back flushes
+		-- that preserve NIA which we can't just yet.
+		if terminate = '1' then
+		    stopping <= '1';
+		    terminated <= '1';
+		end if;
+	    end if;
+	end if;
     end process;
 
     dbg_gpr_addr <= gspr_index;
@@ -238,15 +237,15 @@ begin
     maybe_log: if LOG_LENGTH > 0 generate
         subtype log_ptr_t is unsigned(LOG_INDEX_BITS - 1 downto 0);
         type log_array_t is array(0 to LOG_LENGTH - 1) of std_ulogic_vector(255 downto 0);
-        signal log_array          : log_array_t;
-        signal log_rd_ptr         : log_ptr_t;
-        signal log_wr_ptr         : log_ptr_t;
-        signal log_toggle         : std_ulogic;
-        signal log_wr_enable      : std_ulogic;
+        signal log_array    : log_array_t;
+        signal log_rd_ptr   : log_ptr_t;
+        signal log_wr_ptr   : log_ptr_t;
+        signal log_toggle   : std_ulogic;
+        signal log_wr_enable : std_ulogic;
         signal log_rd_ptr_latched : log_ptr_t;
-        signal log_rd             : std_ulogic_vector(255 downto 0);
-        signal log_dmi_reading    : std_ulogic;
-        signal log_dmi_read_done  : std_ulogic;
+        signal log_rd       : std_ulogic_vector(255 downto 0);
+        signal log_dmi_reading : std_ulogic;
+        signal log_dmi_read_done : std_ulogic;
 
         function select_dword(data : std_ulogic_vector(255 downto 0);
                               addr : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is

core_dram_tb.vhdl

@@ -9,7 +9,7 @@ use work.utils.all;
 
 entity core_dram_tb is
     generic (
-        MEMORY_SIZE    : natural := (384*1024);
+	MEMORY_SIZE    : natural := (384*1024);
         MAIN_RAM_FILE  : string  := "main_ram.bin";
         DRAM_INIT_FILE : string  := "";
         DRAM_INIT_SIZE : natural := 16#c000#
@@ -57,25 +57,25 @@ architecture behave of core_dram_tb is
 begin
 
     soc0: entity work.soc
-        generic map(
-            SIM => true,
-            MEMORY_SIZE => MEMORY_SIZE,
-            RAM_INIT_FILE => MAIN_RAM_FILE,
+	generic map(
+	    SIM => true,
+	    MEMORY_SIZE => MEMORY_SIZE,
+	    RAM_INIT_FILE => MAIN_RAM_FILE,
             HAS_DRAM => true,
-            DRAM_SIZE => 256 * 1024 * 1024,
+	    DRAM_SIZE => 256 * 1024 * 1024,
             DRAM_INIT_SIZE => ROM_SIZE,
-            CLK_FREQ => 100000000,
+	    CLK_FREQ => 100000000,
             HAS_SPI_FLASH    => true,
             SPI_FLASH_DLINES => 4,
             SPI_FLASH_OFFSET => 0
-            )
-        port map(
-            rst => soc_rst,
-            system_clk => system_clk,
-            wb_dram_in => wb_dram_in,
-            wb_dram_out => wb_dram_out,
-            wb_ext_io_in => wb_ext_io_in,
-            wb_ext_io_out => wb_ext_io_out,
+	    )
+	port map(
+	    rst => soc_rst,
+	    system_clk => system_clk,
+	    wb_dram_in => wb_dram_in,
+	    wb_dram_out => wb_dram_out,
+	    wb_ext_io_in => wb_ext_io_in,
+	    wb_ext_io_out => wb_ext_io_out,
             wb_ext_is_dram_csr => wb_ext_is_dram_csr,
             wb_ext_is_dram_init => wb_ext_is_dram_init,
             spi_flash_sck     => spi_sck,
@@ -83,8 +83,8 @@ begin
             spi_flash_sdat_o  => spi_sdat_o,
             spi_flash_sdat_oe => spi_sdat_oe,
             spi_flash_sdat_i  => spi_sdat_i,
-            alt_reset => core_alt_reset
-            );
+	    alt_reset => core_alt_reset
+	    );
 
         flash: entity work.s25fl128s
         generic map (
@@ -121,7 +121,6 @@ begin
             DRAM_ABITS => 24,
             DRAM_ALINES => 1,
             DRAM_DLINES => 16,
-            DRAM_CKLINES => 1,
             DRAM_PORT_WIDTH => 128,
             PAYLOAD_FILE => DRAM_INIT_FILE,
             PAYLOAD_SIZE => ROM_SIZE
@@ -143,18 +142,18 @@ begin
 
     clk_process: process
     begin
-        clk <= '0';
-        wait for clk_period/2;
-        clk <= '1';
-        wait for clk_period/2;
+	clk <= '0';
+	wait for clk_period/2;
+	clk <= '1';
+	wait for clk_period/2;
     end process;
 
     rst_process: process
     begin
-        rst <= '1';
-        wait for 10*clk_period;
-        rst <= '0';
-        wait;
+	rst <= '1';
+	wait for 10*clk_period;
+	rst <= '0';
+	wait;
     end process;