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fpu-init
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divider-init
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caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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microwatt/asic
History
Anton Blanchard ace41e5153 ASIC: Reduce multiplier from 4 to 2 cycles 
Our sky130 gate level multiply/adder now makes timing with a single
register stage.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 		2 years ago
..
behavioural ASIC: Reduce multiplier from 4 to 2 cycles 2 years ago
cache_ram.vhdl Add arrays for ASIC flow 2 years ago
main_bram.vhdl Move register stage back after the RAM 2 years ago
microwatt_asic-verilator.cpp Add ASIC target 2 years ago
multiply.vhdl ASIC: Reduce multiplier from 4 to 2 cycles 2 years ago
register_file.vhdl Add arrays for ASIC flow 2 years ago
top-asic.vhdl Add simplebus 2 years ago