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microwatt
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fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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microwatt/litedram/gen-src/sdram_init
History
Matt Johnston 08021ae28e litedram: set Makefile -Werror 
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 		2 years ago
..
include litedram: Update generator to work with latest LiteX 4 years ago
libc litedram: Add support for Microwatt-initialized controller 4 years ago
Makefile litedram: set Makefile -Werror 2 years ago
bin2hex.py litedram: Add basic support for LiteX LiteDRAM 4 years ago
head.S litedram: Update generator to work with latest LiteX 4 years ago
main.c Add support for more spansion flash 3 years ago
sdram_init.lds.S soc: Rework interconnect 4 years ago