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Matt Johnston 8901e84d8d litedram: Add orangecrab-85-0.2 target ... Parameters are based on https://github.com/gregdavill/OrangeCrab-test-sw/blob/main/hw/OrangeCrab-bitstream.py and litex-boards orangecrab.py rtt_nom and cmd_delay are overridden for OrangeCrab, we do the same here. Generated with litedram and litex 62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.") add2746a ("tools/litex_cli: Rename wb to bus.") Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>		2 years ago
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sdram_init	litedram: set Makefile -Werror	2 years ago
acorn-cle-215.yml	litedram: disable block_until_ready, regenerate	2 years ago
arty.yml	litedram: disable block_until_ready, regenerate	2 years ago
dram-init-mem.vhdl	Make wishbone addresses be in units of doublewords or words	3 years ago
generate.py	litedram: Add orangecrab-85-0.2 target	2 years ago
genesys2.yml	litedram: disable block_until_ready, regenerate	2 years ago
nexys-video.yml	litedram: disable block_until_ready, regenerate	2 years ago
no-init-mem.vhdl	litedram: Split the init memory from the main wrapper	4 years ago
orangecrab-85-0.2.yml	litedram: Add orangecrab-85-0.2 target	2 years ago
sim.yml	litedram: disable block_until_ready, regenerate	2 years ago
wukong-v2.yml	litedram: disable block_until_ready, regenerate	2 years ago