A tiny Open POWER ISA softcore written in VHDL 2008
 
 
 
 
 
 
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Paul Mackerras 10f4be4309 tests: Add a test for privileged instruction interrupts
This adds a test that tries to execute various privileged instructions
with MSR[PR] = 1.  This also incidentally tests some of the MSR bit
manipulations.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
constraints Initial support for ghdl synthesis
fpga Add a few FFs on the RX input to avoid metastability issues
hello_world hello_world: Use Makefile automatic variables
media Add title image
micropython Update micropython
openocd Initial support for ghdl synthesis
rust_lib_demo rust_lib_demo: Remove bin2hex.py
scripts Add VHDL TAGS
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
tests tests: Add a test for privileged instruction interrupts
.gitignore Add VHDL TAGS
.travis.yml Allow a full make check on Travis
LICENSE Initial import of microwatt
Makefile Plumb insn_type through to loadstore1
Makefile.synth make the sources volume mount SELinux friendly
README.md README: hello world needs 16KB of RAM
cache_ram.vhdl dcache: Introduce an extra cycle latency to make timing
common.vhdl dcache: Implement the dcbz instruction
control.vhdl execute: Implement bypass from output of execute1 to input
core.vhdl loadstore1: Move logic from dcache to loadstore1
core_debug.vhdl fetch/icache: Fit icache in BRAM
core_tb.vhdl Reduce simulated and default FPGA RAM to 384kB
countzero.vhdl countzero: Add a register to help make timing
countzero_tb.vhdl countzero: Add a register to help make timing
cr_file.vhdl Dump CTR, LR and CR on sim termination, and update our tests
cr_hazard.vhdl sprs: Store common SPRs in register file
crhelpers.vhdl crhelpers: Constraint "crnum" integer
dcache.vhdl dcache: Implement the dcbz instruction
dcache_tb.vhdl loadstore1: Move logic from dcache to loadstore1
decode1.vhdl dcache: Implement the dcbz instruction
decode2.vhdl Plumb insn_type through to loadstore1
decode_types.vhdl Remove sim_config instruction
divider.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
divider_tb.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl ram: Rework main RAM interface
dmi_dtm_xilinx.vhdl Don't reset JTAG request register asynchronously
execute1.vhdl Plumb insn_type through to loadstore1
fetch1.vhdl fetch/icache: Fit icache in BRAM
fetch2.vhdl fetch2: Remove blank line
glibc_random.vhdl Reformat glibc_random
glibc_random_helpers.vhdl Reformat glibc_random
gpr_hazard.vhdl execute: Implement bypass from output of execute1 to input
helpers.vhdl execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions
icache.vhdl Fix a ghdlsynth issue in icache
icache_tb.vhdl ram: Rework main RAM interface
icache_test.bin icache_tb: Improve test and include test file
insn_helpers.vhdl Implement CRNOR and friends
loadstore1.vhdl dcache: Implement the dcbz instruction
logical.vhdl execute: Move popcnt and prty instructions into the logical unit
microwatt.core Set default RAM to be 16K in microwatt.core
multiply.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
multiply_tb.vhdl execute1: Remember dest GPR, RC, OE, XER for slow operations
plru.vhdl plru: Improve sensitivity list
plru_tb.vhdl plru: Add a simple PLRU module
ppc_fx_insns.vhdl sprs: Store common SPRs in register file
register_file.vhdl Fix ghdlsynth issue in register file
rotator.vhdl Add a rotate/mask/shift unit and use it in execute1
rotator_tb.vhdl Add a rotate/mask/shift unit and use it in execute1
sim_bram.vhdl ram: Rework main RAM interface
sim_bram_helpers.vhdl ram: Rework main RAM interface
sim_bram_helpers_c.c Consolidate VHPI code
sim_console.vhdl Reformat sim_console
sim_console_c.c Consolidate VHPI code
sim_jtag.vhdl Add jtag support in simulation via a socket
sim_jtag_socket.vhdl Add jtag support in simulation via a socket
sim_jtag_socket_c.c Consolidate VHPI code
sim_uart.vhdl Share soc.vhdl between FPGA and sim
sim_vhpi_c.c Consolidate VHPI code
sim_vhpi_c.h Consolidate VHPI code
soc.vhdl Removed unused core_terminated signal
utils.vhdl Add log2ceil and use it in bram code
wishbone_arbiter.vhdl wb_arbiter: Early master selection
wishbone_bram_tb.bin ram: Rework main RAM interface
wishbone_bram_tb.vhdl ram: Rework main RAM interface
wishbone_bram_wrapper.vhdl Add log2ceil and use it in bram code
wishbone_debug_master.vhdl wb_debug: Add wishbone pipelining support
wishbone_types.vhdl wb_arbiter: Make arbiter size parametric
writeback.vhdl execute1: Simplify the interrupt logic a little

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or podman images. Read through the Makefile for details.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)