matthew1kalasky3
/
microwatt
forked from cores/microwatt
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
A tiny Open POWER ISA softcore written in VHDL 2008
349 Commits
31 Branches
0 Tags
65 MiB
Verilog 78.4%
VHDL 16.6%
C 3.7%
Assembly 0.6%
Makefile 0.3%
Other 0.2%
 
 
 
 
 
 
Go to file
Paul Mackerras 23ade0b1c3 decode2: Minor cleanup 
Remove unused variable is_reg in decode_input_reg_a.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
fpga ram: Rework main RAM interface
hello_world Rebuild hello world assuming a 50MHz clock
media Add title image
scripts ram: Rework main RAM interface
sim-unisim Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
tests Initial import of microwatt
.gitignore Update gitignore for new test bench build files
.travis.yml Allow a full make check on Travis
LICENSE Initial import of microwatt
Makefile sprs: Store common SPRs in register file
README.md ram: Rework main RAM interface
cache_ram.vhdl dcache: Introduce an extra cycle latency to make timing
common.vhdl sprs: Store common SPRs in register file
control.vhdl sprs: Store common SPRs in register file
core.vhdl sprs: Store common SPRs in register file
core_debug.vhdl fetch/icache: Fit icache in BRAM
core_tb.vhdl ram: Rework main RAM interface
countzero.vhdl countzero: Reorganize to have fewer levels of logic and fewer LUTs
countzero_tb.vhdl countzero: Add a testbench
cr_file.vhdl Add basic XER support
cr_hazard.vhdl sprs: Store common SPRs in register file
crhelpers.vhdl crhelpers: Constraint "crnum" integer
dcache.vhdl Add basic XER support
dcache_tb.vhdl ram: Rework main RAM interface
decode1.vhdl sprs: Store common SPRs in register file
decode2.vhdl decode2: Minor cleanup
decode_types.vhdl sprs: Store common SPRs in register file
divider.vhdl divider: Fix overflow calculation
divider_tb.vhdl writeback: Do data formatting and condition recording in writeback
dmi_dtm_dummy.vhdl Fix build issue in dmi_dtm_dummy.vhdl
dmi_dtm_tb.vhdl ram: Rework main RAM interface
dmi_dtm_xilinx.vhdl Don't reset JTAG request register asynchronously
execute1.vhdl sprs: Store common SPRs in register file
fetch1.vhdl fetch/icache: Fit icache in BRAM
fetch2.vhdl fetch2: Remove blank line
glibc_random.vhdl Reformat glibc_random
glibc_random_helpers.vhdl Reformat glibc_random
gpr_hazard.vhdl sprs: Store common SPRs in register file
helpers.vhdl execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions
icache.vhdl Move log2/ispow2 to a utils package
icache_tb.vhdl ram: Rework main RAM interface
icache_test.bin icache_tb: Improve test and include test file
insn_helpers.vhdl Add basic XER support
loadstore1.vhdl Add basic XER support
logical.vhdl Consolidate logical instructions
microwatt.core ram: Rework main RAM interface
multiply.vhdl Add basic XER support
multiply_tb.vhdl writeback: Do data formatting and condition recording in writeback
plru.vhdl plru: Improve sensitivity list
plru_tb.vhdl plru: Add a simple PLRU module
ppc_fx_insns.vhdl sprs: Store common SPRs in register file
register_file.vhdl sprs: Store common SPRs in register file
rotator.vhdl Add a rotate/mask/shift unit and use it in execute1
rotator_tb.vhdl Add a rotate/mask/shift unit and use it in execute1
sim_bram.vhdl ram: Rework main RAM interface
sim_bram_helpers.vhdl ram: Rework main RAM interface
sim_bram_helpers_c.c ram: Rework main RAM interface
sim_console.vhdl Reformat sim_console
sim_console_c.c Make sim poll non-blocking
sim_jtag.vhdl Add jtag support in simulation via a socket
sim_jtag_socket.vhdl Add jtag support in simulation via a socket
sim_jtag_socket_c.c debug/sim: Make connect/disconnect messages quieter
sim_uart.vhdl Share soc.vhdl between FPGA and sim
soc.vhdl wb_arbiter: Make arbiter size parametric
utils.vhdl Move log2/ispow2 to a utils package
wishbone_arbiter.vhdl wb_arbiter: Early master selection
wishbone_bram_tb.bin ram: Rework main RAM interface
wishbone_bram_tb.vhdl ram: Rework main RAM interface
wishbone_bram_wrapper.vhdl ram: Ack stores early
wishbone_debug_master.vhdl wb_debug: Add wishbone pipelining support
wishbone_types.vhdl wb_arbiter: Make arbiter size parametric
writeback.vhdl sprs: Store common SPRs in register file

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com
git clone https://github.com/mikey/micropython
cd micropython
git checkout powerpc
cd ports/powerpc
make -j$(nproc)
cd ../../../
  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=8192 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)