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Paul Mackerras
3d4712ad43
This adds a direct-mapped TLB to the icache, with 64 entries by default. Execute1 now sends a "virt_mode" signal from MSR[IR] to fetch1 along with redirects to indicate whether instruction addresses should be translated through the TLB, and fetch1 sends that on to icache. Similarly a "priv_mode" signal is sent to indicate the privilege mode for instruction fetches. This means that changes to MSR[IR] or MSR[PR] don't take effect until the next redirect, meaning an isync, rfid, branch, etc. The icache uses a hash of the effective address (i.e. next instruction address) to index the TLB. The hash is an XOR of three fields of the address; with a 64-entry TLB, the fields are bits 12--17, 18--23 and 24--29 of the address. TLB invalidations simply invalidate the indexed TLB entry without checking the contents. If the icache detects a TLB miss with virt_mode=1, it will send a fetch_failed indication through fetch2 to decode1, which will turn it into a special OP_FETCH_FAILED opcode with unit=LDST. That will get sent down to loadstore1 which will currently just raise a Instruction Storage Interrupt (0x400) exception. One bit in the PTE obtained from the TLB is used to check whether an instruction access is allowed -- the privilege bit (bit 3). If bit 3 is 1 and priv_mode=0, then a fetch_failed indication is sent down to fetch2 and to decode1, which generates an OP_FETCH_FAILED. Any PTEs with PTE bit 0 (EAA[3]) clear or bit 8 (R) clear should not be put into the iTLB since such PTEs would not allow execution by any context. Tlbie operations get sent from mmu to icache over a new connection. Unfortunately the privileged instruction tests are broken for now. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
5 years ago | |
|---|---|---|
| constraints | 5 years ago | |
| fpga | 5 years ago | |
| hello_world | 5 years ago | |
| media | 5 years ago | |
| micropython | 5 years ago | |
| openocd | 5 years ago | |
| rust_lib_demo | 5 years ago | |
| scripts | 5 years ago | |
| sim-unisim | 5 years ago | |
| tests | 5 years ago | |
| .gitignore | 5 years ago | |
| .travis.yml | 5 years ago | |
| LICENSE | 5 years ago | |
| Makefile | 5 years ago | |
| Makefile.synth | 5 years ago | |
| README.md | 5 years ago | |
| cache_ram.vhdl | 5 years ago | |
| common.vhdl | 5 years ago | |
| control.vhdl | 5 years ago | |
| core.vhdl | 5 years ago | |
| core_debug.vhdl | 5 years ago | |
| core_tb.vhdl | 5 years ago | |
| countzero.vhdl | 5 years ago | |
| countzero_tb.vhdl | 5 years ago | |
| cr_file.vhdl | 5 years ago | |
| cr_hazard.vhdl | 5 years ago | |
| crhelpers.vhdl | 5 years ago | |
| dcache.vhdl | 5 years ago | |
| dcache_tb.vhdl | 5 years ago | |
| decode1.vhdl | 5 years ago | |
| decode2.vhdl | 5 years ago | |
| decode_types.vhdl | 5 years ago | |
| divider.vhdl | 5 years ago | |
| divider_tb.vhdl | 5 years ago | |
| dmi_dtm_dummy.vhdl | 5 years ago | |
| dmi_dtm_tb.vhdl | 5 years ago | |
| dmi_dtm_xilinx.vhdl | 5 years ago | |
| execute1.vhdl | 5 years ago | |
| fetch1.vhdl | 5 years ago | |
| fetch2.vhdl | 5 years ago | |
| glibc_random.vhdl | 5 years ago | |
| glibc_random_helpers.vhdl | 5 years ago | |
| gpr_hazard.vhdl | 5 years ago | |
| helpers.vhdl | 5 years ago | |
| icache.vhdl | 5 years ago | |
| icache_tb.vhdl | 5 years ago | |
| icache_test.bin | 5 years ago | |
| insn_helpers.vhdl | 5 years ago | |
| loadstore1.vhdl | 5 years ago | |
| logical.vhdl | 5 years ago | |
| microwatt.core | 5 years ago | |
| mmu.vhdl | 5 years ago | |
| multiply.vhdl | 5 years ago | |
| multiply_tb.vhdl | 5 years ago | |
| plru.vhdl | 5 years ago | |
| plru_tb.vhdl | 5 years ago | |
| ppc_fx_insns.vhdl | 5 years ago | |
| register_file.vhdl | 5 years ago | |
| rotator.vhdl | 5 years ago | |
| rotator_tb.vhdl | 5 years ago | |
| sim_bram.vhdl | 5 years ago | |
| sim_bram_helpers.vhdl | 5 years ago | |
| sim_bram_helpers_c.c | 5 years ago | |
| sim_console.vhdl | 5 years ago | |
| sim_console_c.c | 5 years ago | |
| sim_jtag.vhdl | 5 years ago | |
| sim_jtag_socket.vhdl | 5 years ago | |
| sim_jtag_socket_c.c | 5 years ago | |
| sim_uart.vhdl | 5 years ago | |
| sim_vhpi_c.c | 5 years ago | |
| sim_vhpi_c.h | 5 years ago | |
| soc.vhdl | 5 years ago | |
| utils.vhdl | 5 years ago | |
| wishbone_arbiter.vhdl | 5 years ago | |
| wishbone_bram_tb.bin | 5 years ago | |
| wishbone_bram_tb.vhdl | 5 years ago | |
| wishbone_bram_wrapper.vhdl | 5 years ago | |
| wishbone_debug_master.vhdl | 5 years ago | |
| wishbone_types.vhdl | 5 years ago | |
| writeback.vhdl | 5 years ago | |
| xics.vhdl | 5 years ago | |
README.md
Microwatt
A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
Simulation using ghdl
You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.
- Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../
A prebuilt micropython image is also available in the micropython/ directory.
-
Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.
If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or podman images. Read through the Makefile for details.
-
Next build microwatt:
git clone https://github.com/antonblanchard/microwatt
cd microwatt
make
- Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin
Or if you were using the pre-built image:
ln -s micropython/firmware.bin main_ram.bin
- Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null
Synthesis on Xilinx FPGAs using Vivado
-
Install Vivado (I'm using the free 2019.1 webpack edition).
-
Setup Vivado paths:
source /opt/Xilinx/Vivado/2019.1/settings64.sh
- Install FuseSoC:
pip3 install --user -U fusesoc
Fedora users can get FuseSoC package via
sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
- Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
- Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex
You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.
- To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt
Testing
- A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check
Issues
This is functional, but very simple. We still have quite a lot to do:
- There are a few instructions still to be implemented
- Need to add caches and bypassing (in progress)
- Need to add supervisor state (in progress)