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A tiny Open POWER ISA softcore written in VHDL 2008
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Benjamin Herrenschmidt 434962bc34 tests: Add updated micropython build with 16550 support 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
.github/workflows
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constraints
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fpga uart: Make 16550 the default
hello_world console: Add support for the 16550 UART
include syscon: Add flag to indicate the timebase frequency
lib console: Add support for the 16550 UART
litedram console: Add support for the 16550 UART
liteeth liteeth: Hook up LiteX LiteEth ethernet controller
media
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micropython tests: Add updated micropython build with 16550 support
openocd flash-arty: update error message ()
rust_lib_demo console: Cleanup console API
scripts uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
sim-unisim
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tests tests: Add updated micropython build with 16550 support
verilator
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.gitignore
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LICENSE
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Makefile uart: Add a simulation model for the 16550 compatible UART
README.md
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cache_ram.vhdl
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common.vhdl ex1: Add SPR_TBU support
control.vhdl core: Use a busy signal rather than a stall
core.vhdl Make LOG_LENGTH configurable per FPGA variant
core_debug.vhdl Make LOG_LENGTH configurable per FPGA variant
core_dram_tb.vhdl soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
core_flash_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel
core_tb.vhdl soc: Don't require dram wishbones signals to be wired by toplevel
countzero.vhdl
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countzero_tb.vhdl
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cr_file.vhdl Add core logging
cr_hazard.vhdl core: Use a busy signal rather than a stall
crhelpers.vhdl
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dcache.vhdl dcache: Reduce back-to-back store latency from 3 cycles to 2
dcache_tb.vhdl
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decode1.vhdl core: Implement a simple branch predictor
decode2.vhdl core: Implement a simple branch predictor
decode_types.vhdl
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divider.vhdl
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divider_tb.vhdl
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dmi_dtm_dummy.vhdl
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dmi_dtm_tb.vhdl
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dmi_dtm_xilinx.vhdl dmi: Add ASYNC_REG attribute on synchronizers ()
dram_tb.vhdl litedram: Improve dram_tb error output
execute1.vhdl ex1: Add SPR_TBU support
fetch1.vhdl core: Implement a simple branch predictor
glibc_random.vhdl
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glibc_random_helpers.vhdl
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gpr_hazard.vhdl core: Use a busy signal rather than a stall
helpers.vhdl
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icache.vhdl icache: Improve latencies when reloading cache lines
icache_tb.vhdl core: Remove fetch2 pipeline stage
icache_test.bin
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insn_helpers.vhdl
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loadstore1.vhdl loadstore1: Reduce busy cycles
logical.vhdl execute1: Reduce width of the result mux to help timing
microwatt.core uart: Make 16550 the default
mmu.vhdl mmu: Take an extra cycle to do TLB invalidations
multiply.vhdl multiply: Move selection of result bits into execute1
multiply_tb.vhdl multiply: Move selection of result bits into execute1
plru.vhdl
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plru_tb.vhdl
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ppc_fx_insns.vhdl core: Implement a simple branch predictor
register_file.vhdl Add core logging
rotator.vhdl
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rotator_tb.vhdl
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sim_16550_uart.vhdl uart: Add a simulation model for the 16550 compatible UART
sim_bram.vhdl
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sim_bram_helpers.vhdl
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sim_bram_helpers_c.c
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sim_console.vhdl
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sim_console_c.c sim_console: Fix polling to check for POLLIN
sim_jtag.vhdl
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sim_jtag_socket.vhdl
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sim_jtag_socket_c.c
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sim_no_flash.vhdl spi: Add simulation support
sim_pp_uart.vhdl uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
sim_vhpi_c.c
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sim_vhpi_c.h
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soc.vhdl uart: Make 16550 the default
spi_flash_ctrl.vhdl spi: Add SPI Flash controller
spi_rxtx.vhdl spi: Add SPI Flash controller
sync_fifo.vhdl
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syscon.vhdl syscon: Add flag to indicate the timebase frequency
utils.vhdl
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wishbone_arbiter.vhdl
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wishbone_bram_tb.bin
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wishbone_bram_tb.vhdl
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wishbone_bram_wrapper.vhdl
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wishbone_debug_master.vhdl
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wishbone_types.vhdl soc: Don't require dram wishbones signals to be wired by toplevel
writeback.vhdl core: Use a busy signal rather than a stall
xics.vhdl xics: Add support for reduced priority field size
xilinx-mult.vhdl multiply: Use DSP48 slices for multiplication on Xilinx FPGAs

README.md

Microwatt

Microwatt

A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.

Simulation using ghdl

MicroPython running on Microwatt

You can try out Microwatt/Micropython without hardware by using the ghdl simulator. If you want to build directly for a hardware target board, see below.

  • Build micropython. If you aren't building on a ppc64le box you will need a cross compiler. If it isn't available on your distro grab the powerpc64le-power8 toolchain from https://toolchains.bootlin.com. You may need to set the CROSS_COMPILE environment variable to the prefix used for your cross compilers. The default is powerpc64le-linux-gnu-.
git clone https://github.com/micropython/micropython.git
cd micropython
cd ports/powerpc
make -j$(nproc)
cd ../../../

A prebuilt micropython image is also available in the micropython/ directory.

  • Microwatt uses ghdl for simulation. Either install this from your distro or build it. Microwatt requires ghdl to be built with the LLVM or gcc backend, which not all distros do (Fedora does, Debian/Ubuntu appears not to). ghdl with the LLVM backend is likely easier to build.

    If building ghdl from scratch is too much for you, the microwatt Makefile supports using Docker or Podman.

  • Next build microwatt:

git clone https://github.com/antonblanchard/microwatt
cd microwatt
make

To build using Docker:

make DOCKER=1

and to build using Podman:

make PODMAN=1
  • Link in the micropython image:
ln -s ../micropython/ports/powerpc/build/firmware.bin main_ram.bin

Or if you were using the pre-built image:

ln -s micropython/firmware.bin main_ram.bin
  • Now run microwatt, sending debug output to /dev/null:
./core_tb > /dev/null

Synthesis on Xilinx FPGAs using Vivado

  • Install Vivado (I'm using the free 2019.1 webpack edition).

  • Setup Vivado paths:

source /opt/Xilinx/Vivado/2019.1/settings64.sh
  • Install FuseSoC:
pip3 install --user -U fusesoc

Fedora users can get FuseSoC package via

sudo dnf copr enable sharkcz/danny
sudo dnf install fusesoc
  • Create a working directory and point FuseSoC at microwatt:
mkdir microwatt-fusesoc
cd microwatt-fusesoc
fusesoc library add microwatt /path/to/microwatt/
  • Build using FuseSoC. For hello world (Replace nexys_video with your FPGA board such as --target=arty_a7-100):
fusesoc run --target=nexys_video microwatt --memory_size=16384 --ram_init_file=/path/to/microwatt/fpga/hello_world.hex

You should then be able to see output via the serial port of the board (/dev/ttyUSB1, 115200 for example assuming standard clock speeds). There is a know bug where initial output may not be sent - try the reset (not programming button) on your board if you don't see anything.

  • To build micropython (currently requires 1MB of BRAM eg an Artix-7 A200):
fusesoc run --target=nexys_video microwatt

Testing

  • A simple test suite containing random execution test cases and a couple of micropython test cases can be run with:
make -j$(nproc) check

Issues

This is functional, but very simple. We still have quite a lot to do:

  • There are a few instructions still to be implemented
  • Need to add caches and bypassing (in progress)
  • Need to add supervisor state (in progress)